Joseph Yedinak
Inventor
Stats
- 2 US patents issued
- 6 US Applications filed
- most recent filing
This is official USPTO record data
Details
- 2 US Patents Issued
- 6 US Applications Filed
- 260 Total Citation Count
- Jan 25, 2019 Most Recent Filing
- Feb 9, 2009 Earliest Filing
Work History
| Patent Owner | Applications Filed | Year |
|---|---|---|
| FAIRCHILD SEMICONDUCTOR CORPORATION | 4
1 | 2009
2013 |
Inventor Addresses
| Address | Duration |
|---|---|
| Mountain Top, PA, US | Sep 18, 14 - Oct 15, 19 |
| Mountaintop, PA, US | Aug 12, 10 - Jul 24, 12 |
Technology Profile
| Technology | Matters | |
|---|---|---|
| G03F: | PHOTOMECHANICAL PRODUCTION OF TEXTURED OR PATTERNED SURFACES, e.g. FOR PRINTING, FOR PROCESSING OF SEMICONDUCTOR DEVICES; MATERIALS THEREFOR; ORIGINALS THEREFOR; APPARATUS SPECIALLY ADAPTED THEREFOR | 1 |
| H01L: | SEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR | 6 |
Patents / Publication
| Patents / Publication # | Year of Publication / Issued | Title | Citations |
|---|---|---|---|
| 10446640 | 2019 | Termination implant enrichment for shielded gate MOSFETS | 0 |
| 10374076 | 2019 | Shield indent trench termination for shielded gate MOSFETs | 0 |
| 2019/0157,383 | 2019 | TERMINATION IMPLANT ENRICHMENT FOR SHIELDED GATE MOSFETS | 0 |
| 10236340 | 2019 | Termination implant enrichment for shielded gate MOSFETs | 0 |
| 2019/0006,512 | 2019 | SHIELD INDENT TRENCH TERMINATION FOR SHIELDED GATE MOSFETS | 0 |
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