Tsai-Ming Yang
Inventor
Stats
- 7 US patents issued
- 13 US Applications filed
- most recent filing
This is official USPTO record data
Details
- 7 US Patents Issued
- 13 US Applications Filed
- 20 Total Citation Count
- Feb 25, 2021 Most Recent Filing
- May 21, 2007 Earliest Filing
Work History
| Patent Owner | Applications Filed | Year |
|---|---|---|
| TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD. | 2
1 2 1 1 | 2011
2013 2014 2015 2016 |
| UNITED MICROELECTRONICS CORP. | 1
2 | 2007
2008 |
| GLOBAL UNICHIP CORPORATION | 2
1 2 1 1 | 2011
2013 2014 2015 2016 |
Inventor Addresses
| Address | Duration |
|---|---|
| HSINCHU CITY, TW | Jan 28, 21 - May 27, 21 |
| Hsinchu, TW | Apr 18, 17 - Aug 29, 23 |
| Tainan City, TW | Feb 14, 13 - Feb 12, 15 |
| Tainan County, TW | Jun 17, 08 - Apr 14, 09 |
| Tainan, TW | Mar 19, 13 - Dec 24, 19 |
Technology Profile
| Technology | Matters | |
|---|---|---|
| G01R: | MEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES | 1 |
| G06F: | ELECTRIC DIGITAL DATA PROCESSING | 1 |
| H01L: | SEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR | 1 |
Patents / Publication
| Patents / Publication # | Year of Publication / Issued | Title | Citations |
|---|---|---|---|
| 11742295 | 2023 | Interface of integrated circuit die and method for arranging interface thereof | 0 |
| 2022/0208,684 | 2022 | INTERFACE OF INTEGRATED CIRCUIT DIE AND METHOD FOR ARRANGING INTERFACE THEREOF | 0 |
| 11336427 | 2022 | Circuit of communication interface between two dies and method to manage communication interface | 0 |
| 11313904 | 2022 | Testing device and testing method | 1 |
| 11169561 | 2021 | Clock data recovery device and method to alternatively adjust phases of outputted clock signals | 0 |
We are sorry but your current selection exceeds the maximum number of portfolios (0) for this membership level.
>
Upgrade to our Level for up to -1 portfolios!.