David G Wontor
Inventor
Stats
- 7 US patents issued
- 8 US Applications filed
- most recent filing
This is official USPTO record data
Details
- 7 US Patents Issued
- 8 US Applications Filed
- 481 Total Citation Count
- Sep 24, 2011 Most Recent Filing
- Apr 18, 2003 Earliest Filing
Work History
| Patent Owner | Applications Filed | Year |
|---|---|---|
| TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD. | 2
| 2005
|
| VLSI TECHNOLOGY LLC | 2
| 2005
|
| NXP USA, INC. | 4
2 2 | 2003
2005 2008 |
| TEXAS INSTRUMENTS INCORPORATED | 2
1 | 2008
2011 |
Inventor Addresses
| Address | Duration |
|---|---|
| Allen, TX | Dec 28, 06 - Dec 28, 06 |
| Allen, TX, US | Nov 24, 09 - Nov 24, 09 |
| Austin, TX | Jan 04, 05 - Jun 19, 08 |
| Austin, TX, US | Oct 21, 04 - Dec 06, 11 |
| DUBLIN, CA, US | Jan 19, 12 - Jan 19, 12 |
| Dublin, CA, US | May 07, 09 - Nov 08, 11 |
Technology Profile
| Technology | Matters | |
|---|---|---|
| G01R: | MEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES | 1 |
| H01L: | SEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR | 8 |
Patents / Publication
| Patents / Publication # | Year of Publication / Issued | Title | Citations |
|---|---|---|---|
| 2012/0013,003 | 2012 | BGA PACKAGE WITH TRACES FOR PLATING PADS UNDER THE CHIP | 2 |
| 8072062 | 2011 | Circuit device with at least partial packaging and method for forming | 2 |
| 8053349 | 2011 | BGA package with traces for plating pads under the chip | 3 |
| 7622309 | 2009 | Mechanical integrity evaluation of low-k devices with bump shear | 11 |
| 2009/0115,072 | 2009 | BGA Package with Traces for Plating Pads Under the Chip | 19 |
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