Simon Edward Willard
Inventor
Stats
- 5 US patents issued
- 76 US Applications filed
- most recent filing
This is official USPTO record data
Details
- 5 US Patents Issued
- 76 US Applications Filed
- 280 Total Citation Count
- Oct 21, 2024 Most Recent Filing
- Jan 10, 2009 Earliest Filing
Work History
| Patent Owner | Applications Filed | Year |
|---|---|---|
| PEREGRINE SEMICONDUCTOR CORPORATION | 3
5 | 2015
2016 |
| APPLIED MICRO CIRCUITS CORPORATION | 1
| 2009
|
Inventor Addresses
| Address | Duration |
|---|---|
| IRVINE, CA, US | Dec 16, 21 - Oct 10, 24 |
| Irvine, CA, US | Jul 15, 10 - Mar 18, 25 |
| San Diego, CA, US | Feb 06, 25 - Feb 06, 25 |
Technology Profile
| Technology | Matters | |
|---|---|---|
| H01G: | CAPACITORS; CAPACITORS, RECTIFIERS, DETECTORS, SWITCHING DEVICES, LIGHT-SENSITIVE OR TEMPERATURE-SENSITIVE DEVICES OF THE ELECTROLYTIC TYPE | 1 |
| H01L: | SEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR | 63 |
| H03B: | GENERATION OF OSCILLATIONS, DIRECTLY OR BY FREQUENCY-CHANGING, BY CIRCUITS EMPLOYING ACTIVE ELEMENTS WHICH OPERATE IN A NON-SWITCHING MANNER; GENERATION OF NOISE BY SUCH CIRCUITS | 2 |
Patents / Publication
| Patents / Publication # | Year of Publication / Issued | Title | Citations |
|---|---|---|---|
| 12255587 | 2025 | Gate drivers for stacked transistor amplifiers | 0 |
| 2025/0072,062 | 2025 | Low Leakage FET | 0 |
| 2025/0063,822 | 2025 | Contact Structures for Dual-Thickness Active Area SOI FETS | 0 |
| 12231087 | 2025 | Body tie optimization for stacked transistor amplifier | 0 |
| 2025/0056,875 | 2025 | Efficient FET Body and Substrate Contacts | 0 |
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