Bruce Whitefield
Inventor
Stats
- 19 US patents issued
- 19 US Applications filed
- most recent filing
This is official USPTO record data
Details
- 19 US Patents Issued
- 19 US Applications Filed
- 222 Total Citation Count
- Nov 8, 2007 Most Recent Filing
- Jul 19, 1991 Earliest Filing
Work History
| Patent Owner | Applications Filed | Year |
|---|---|---|
| LSI LOGIC CORPORATION | 1
1 1 1 1 2 2 | 1991
1994 1995 2001 2002 2003 2007 |
| BELL SEMICONDUCTOR, LLC | 3
2 6 8 2 2 2 | 2001
2002 2003 2004 2005 2006 2007 |
Inventor Addresses
| Address | Duration |
|---|---|
| Camas, WA | Dec 17, 02 - Dec 02, 08 |
| Camas, WA, US | Feb 03, 05 - Sep 21, 10 |
| Menlo Park, CA | Jan 03, 95 - Aug 05, 97 |
Technology Profile
| Technology | Matters | |
|---|---|---|
| B24B: | MACHINES, DEVICES, OR PROCESSES FOR GRINDING OR POLISHING | 1 |
| G01B: | MEASURING LENGTH, THICKNESS OR SIMILAR LINEAR DIMENSIONS; MEASURING ANGLES; MEASURING AREAS; MEASURING IRREGULARITIES OF SURFACES OR CONTOURS | 1 |
| G01N: | INVESTIGATING OR ANALYSING MATERIALS BY DETERMINING THEIR CHEMICAL OR PHYSICAL PROPERTIES | 1 |
Patents / Publication
| Patents / Publication # | Year of Publication / Issued | Title | Citations |
|---|---|---|---|
| 7799166 | 2010 | Wafer edge expose alignment method | 3 |
| 7653523 | 2010 | Method for calculating high-resolution wafer parameter profiles | 0 |
| 7560292 | 2009 | Voltage contrast monitor for integrated circuit defects | 0 |
| 7460211 | 2008 | Apparatus for wafer patterning to reduce edge exclusion zone | 9 |
| 2008/0061,805 | 2008 | VOLTAGE CONTRAST MONITOR FOR INTEGRATED CIRCUIT DEFECTS | 1 |
We are sorry but your current selection exceeds the maximum number of portfolios (0) for this membership level.
>
Upgrade to our Level for up to -1 portfolios!.