Runsheng Wang
Inventor
Stats
- 13 US patents issued
- 20 US Applications filed
- most recent filing
This is official USPTO record data
Details
- 13 US Patents Issued
- 20 US Applications Filed
- 102 Total Citation Count
- Jan 31, 2024 Most Recent Filing
- Sep 25, 2010 Earliest Filing
Work History
Patent Owner | Applications Filed | Year |
---|---|---|
SEMICONDUCTOR MANUFACTURING INTERNATIONAL (SHANGHAI) CORPORATION | 2
10 1 | 2010
2011 2012 |
PEKING UNIVERSITY | 13
5 1 1 | 2011
2012 2013 2014 |
Inventor Addresses
Address | Duration |
---|---|
Beijing, CN | May 10, 12 - Apr 14, 20 |
Shenzhen, CN | Aug 15, 24 - Aug 15, 24 |
Technology Profile
Technology | Matters | |
---|---|---|
B08B: | CLEANING IN GENERAL; PREVENTION OF FOULING IN GENERAL | 1 |
B82Y: | SPECIFIC USES OR APPLICATIONS OF NANO-STRUCTURES; MEASUREMENT OR ANALYSIS OF NANO-STRUCTURES; MANUFACTURE OR TREATMENT OF NANO-STRUCTURES | 7 |
C09K: | MATERIALS FOR APPLICATIONS NOT OTHERWISE PROVIDED FOR; APPLICATIONS OF MATERIALS NOT OTHERWISE PROVIDED FOR | 1 |
Patents / Publication
Patents / Publication # | Year of Publication / Issued | Title | Citations |
---|---|---|---|
2024/0273,274 | 2024 | Method for establishing transistor statistical model based on artificial neural network system | 0 |
10621386 | 2020 | Method of bias temperature instability calculation and prediction for MOSFET and FinFET | 0 |
9478641 | 2016 | Method for fabricating FinFET with separated double gates on bulk silicon | 2 |
2016/0153,923 | 2016 | METHOD FOR EXTRACTING TRAP TIME CONSTANT OF GATE DIELECTRIC LAYER IN SEMICONDUCTOR DEVICE | 0 |
2015/0236,130 | 2015 | METHOD FOR FABRICATING FINFET WITH SEPARATED DOUBLE GATES ON BULK SILICON | 4 |
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