Chen-Wen Tsai
Inventor
Stats
- 10 US patents issued
- 12 US Applications filed
- most recent filing
This is official USPTO record data
Details
- 10 US Patents Issued
- 12 US Applications Filed
- 195 Total Citation Count
- Jun 4, 2005 Most Recent Filing
- May 4, 1992 Earliest Filing
Work History
Patent Owner | Applications Filed | Year |
---|---|---|
INDUSTRIAL TECHNOLOGY RESEARCH INSTITUTE | 1
| 1992
|
SILICON INTEGRATED SYSTEMS CORP. | 2
2 1 | 2000
2001 2002 |
TAICHI HOLDINGS, LLC | 1
2 1 1 | 1999
2000 2001 2002 |
GSI TECHNOLOGY INC. | 1
| 2005
|
Inventor Addresses
Address | Duration |
---|---|
Hsin-Chu, TW | Sep 12, 00 - Sep 12, 00 |
Hsinchu City, TW | Dec 07, 06 - Dec 07, 06 |
Hsinchu, JP | Nov 07, 02 - Nov 07, 02 |
Hsinchu, TW | Jun 15, 93 - Jan 04, 05 |
Technology Profile
Technology | Matters | |
---|---|---|
B65D: | CONTAINERS FOR STORAGE OR TRANSPORT OF ARTICLES OR MATERIALS, e.g. BAGS, BARRELS, BOTTLES, BOXES, CANS, CARTONS, CRATES, DRUMS, JARS, TANKS, HOPPERS, FORWARDING CONTAINERS; ACCESSORIES, CLOSURES, OR FITTINGS THEREFOR; PACKAGING ELEMENTS; PACKAGES | 1 |
C04B: | LIME; MAGNESIA; SLAG; CEMENTS; COMPOSITIONS THEREOF, e.g. MORTARS, CONCRETE OR LIKE BUILDING MATERIALS; ARTIFICIAL STONE; CERAMICS | 1 |
G01R: | MEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES | 1 |
Patents / Publication
Patents / Publication # | Year of Publication / Issued | Title | Citations |
---|---|---|---|
2006/0273,441 | 2006 | Assembly structure and method for chip scale package | 0 |
6838756 | 2005 | Chip-packaging substrate | 0 |
6653574 | 2003 | Multi-layered substrate with a built-in capacitor design and a method of making the same | 6 |
6524942 | 2003 | Bond pad structure and its method of fabricating | 9 |
6509646 | 2003 | Apparatus for reducing an electrical noise inside a ball grid array package | 9 |
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