Gaurav Thareja
Inventor
Stats
- 2 US patents issued
- 75 US Applications filed
- most recent filing
This is official USPTO record data
Details
- 2 US Patents Issued
- 75 US Applications Filed
- 378 Total Citation Count
- Oct 16, 2024 Most Recent Filing
- Jul 27, 2012 Earliest Filing
Work History
| Patent Owner | Applications Filed | Year |
|---|---|---|
| INTEL CORPORATION | 4
1 | 2012
2017 |
Inventor Addresses
| Address | Duration |
|---|---|
| Hillsboro, OR, US | Jan 30, 14 - Nov 14, 24 |
| Redmond, WA, US | May 06, 21 - Aug 16, 22 |
| SANTA CLARA, CA, US | Apr 30, 20 - Apr 30, 20 |
| Santa Clara, CA, US | Aug 15, 19 - Jan 30, 25 |
Technology Profile
| Technology | Matters | |
|---|---|---|
| C23C: | COATING METALLIC MATERIAL; COATING MATERIAL WITH METALLIC MATERIAL; SURFACE TREATMENT OF METALLIC MATERIAL BY DIFFUSION INTO THE SURFACE, BY CHEMICAL CONVERSION OR SUBSTITUTION; COATING BY VACUUM EVAPORATION, BY SPUTTERING, BY ION IMPLANTATION OR BY CHEMICAL VAPOUR DEPOSITION, IN GENERAL | 1 |
| G06F: | ELECTRIC DIGITAL DATA PROCESSING | 8 |
| G11C: | STATIC STORES | 11 |
Patents / Publication
| Patents / Publication # | Year of Publication / Issued | Title | Citations |
|---|---|---|---|
| 2025/0040,146 | 2025 | PLANAR FERROELECTRIC MEMORY DEVICE | 0 |
| 12200941 | 2025 | Pillar capacitor and method of fabricating such | 0 |
| 2024/0421,229 | 2024 | DOPED POLAR LAYERS AND SEMICONDUCTOR DEVICE INCORPORATING SAME | 0 |
| 2024/0379,453 | 2024 | SELF-ALIGNED 3-D EPITAXIAL STRUCTURES FOR MOS DEVICE FABRICATION | 0 |
| 2024/0380,403 | 2024 | METHOD OF FORMING A MAJORITY GATE BASED LOW POWER FERROELECTRIC BASED ADDER WITH RESET MECHANISM | 0 |
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