Yasuhiro Takai

Inventor

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Work History

Patent OwnerApplications FiledYear
LONGITUDE SEMICONDUCTOR S.A.R.L.
1
4
2
4
2
6
4
14
2
4
2
1
2
1998
2001
2002
2004
2005
2006
2007
2008
2009
2012
2013
2014
2015
NEC CORPORATION
1
1
1989
1994
RENESAS ELECTRONICS CORPORATION
1
1
1
1
1
1994
1995
1997
1998
2000
ELPIDA MEMORY, INC.
1
1
2
1
1991
2007
2008
2009
NEC ELECTRONICS CORPORATION
1
1
1999
2000
MICRON TECHNOLOGY, INC.
2
2
1
1
2008
2009
2015
2016
SHARP KABUSHIKI KAISHA
1
1
1
1
2
2
1
1
2
4
6
15
27
5
1985
1988
1989
1990
1993
1994
1995
1998
2002
2004
2005
2006
2007
2008
PS4 LUXCO S.A.R.L.
2
2
1995
2002

Inventor Addresses

AddressDuration
Kanagawa, JPSep 03, 19 - Dec 22, 20
Nara, JPAug 25, 05 - Jun 26, 12
Sagamihara, JPAug 30, 16 - Apr 10, 25
Sakurai, JPJan 13, 87 - May 31, 11
Sakurai--shi, JPNov 13, 08 - Nov 13, 08
Sakurai-shi, JPMay 22, 03 - Oct 23, 08
Tokyo, JPApr 02, 91 - Feb 14, 17

Technology Profile

Technology Matters
B41F: PRINTING MACHINES OR PRESSES 4
B41J: TYPEWRITERS; SELECTIVE PRINTING MECHANISMS, i.e. MECHANISMS PRINTING OTHERWISE THAN FROM A FORME; CORRECTION OF TYPOGRAPHICAL ERRORS 2
B65H: HANDLING THIN OR FILAMENTARY MATERIAL, e.g. SHEETS, WEBS, CABLES 12

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Patents / Publication

Patents / Publication #Year of Publication / IssuedTitleCitations
2025/0118,3562025APPARATUS INCLUDING CLOCK INPUT BUFFER0
112517962022Phase lock circuitry using frequency detection1
2021/0075,4282021PHASE LOCK CIRCUITRY USING FREQUENCY DETECTION0
2021/0058,0902021PHASE LOCKED LOOP CIRCUIT0
109312872021Phase locked loop circuit1

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