RAJA SWAMINATHAN
Inventor
Stats
- 0 US patents issued
- 31 US Applications filed
- most recent filing
This is official USPTO record data
Details
- 0 US Patents Issued
- 31 US Applications Filed
- 22 Total Citation Count
- Nov 12, 2024 Most Recent Filing
- Oct 30, 2020 Earliest Filing
Work History
No Work History Available.Inventor Addresses
| Address | Duration |
|---|---|
| AUSTIN, TX, US | Feb 17, 22 - Apr 04, 24 |
| Austin, TX, US | Mar 30, 23 - Apr 03, 25 |
| Santa Clara, CA, US | Jun 22, 23 - Feb 27, 25 |
Technology Profile
| Technology | Matters | |
|---|---|---|
| B23K: | SOLDERING OR UNSOLDERING; WELDING; CLADDING OR PLATING BY SOLDERING OR WELDING; CUTTING BY APPLYING HEAT LOCALLY, e.g. FLAME CUTTING; WORKING BY LASER BEAM | 1 |
| G02B: | OPTICAL ELEMENTS, SYSTEMS, OR APPARATUS | 2 |
| G05F: | SYSTEMS FOR REGULATING ELECTRIC OR MAGNETIC VARIABLES | 2 |
Patents / Publication
| Patents / Publication # | Year of Publication / Issued | Title | Citations |
|---|---|---|---|
| 2025/0112,047 | 2025 | CHIP-ON-WAFER FACE-TO-BACK HYBRID BONDING WITHOUT SUPPORT CARRIER | 0 |
| 12266611 | 2025 | Mixed density interconnect architectures using hybrid fan-out | 0 |
| 2025/0070,031 | 2025 | 3D SEMICONDUCTOR PACKAGE WITH DIE-MOUNTED VOLTAGE REGULATOR | 0 |
| 12165981 | 2024 | 3D semiconductor package with die-mounted voltage regulator | 0 |
| 2024/0404,897 | 2024 | CHIP COMPLEX WITH EMBEDDED INTERPOSER | 0 |
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