Ramacharan Sundararaman
Inventor
Stats
- 11 US patents issued
- 31 US Applications filed
- most recent filing
This is official USPTO record data
Details
- 11 US Patents Issued
- 31 US Applications Filed
- 162 Total Citation Count
- Sep 13, 2023 Most Recent Filing
- Dec 27, 2000 Earliest Filing
Work History
| Patent Owner | Applications Filed | Year |
|---|---|---|
| INTEL CORPORATION | 2
2 2 7 3 4 | 2000
2007 2009 2011 2012 2014 |
Inventor Addresses
| Address | Duration |
|---|---|
| Aloha, OR | Aug 03, 04 - Aug 03, 04 |
| Aloha, OR, US | Jun 27, 02 - Jun 27, 02 |
| Hillsboro, OR, US | Jun 18, 09 - Oct 10, 23 |
| Portland, OR, US | Apr 04, 19 - Dec 21, 21 |
| San Jose, CA, US | Feb 23, 21 - Mar 13, 25 |
| Santa Clara, CA, US | Jul 03, 14 - Jul 03, 14 |
Technology Profile
| Technology | Matters | |
|---|---|---|
| G05B: | CONTROL OR REGULATING SYSTEMS IN GENERAL; FUNCTIONAL ELEMENTS OF SUCH SYSTEMS; MONITORING OR TESTING ARRANGEMENTS FOR SUCH SYSTEMS OR ELEMENTS | 1 |
| G06F: | ELECTRIC DIGITAL DATA PROCESSING | 29 |
| G06N: | COMPUTER SYSTEMS BASED ON SPECIFIC COMPUTATIONAL MODELS | 5 |
Patents / Publication
| Patents / Publication # | Year of Publication / Issued | Title | Citations |
|---|---|---|---|
| 2025/0086,136 | 2025 | Mechanism To Improve The Reliability Of Sideband In Chiplets | 0 |
| 2024/0427,709 | 2024 | APPARATUS AND METHODS FOR REDUCING LATENCIES ASSOCIATED WITH LINK STATE TRANSITIONS WITHIN DIE INTERCONNECT ARCHITECTURES | 0 |
| 12174757 | 2024 | Apparatus and methods for reducing latencies associated with link state transitions within die interconnect architectures | 0 |
| 11927932 | 2024 | System and method to manage power to a desired power profile | 0 |
| 11921904 | 2024 | System and methods for firmware security mechanism | 0 |
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