Ke-Ying Su
Inventor
Stats
- 30 US patents issued
- 48 US Applications filed
- most recent filing
This is official USPTO record data
Details
- 30 US Patents Issued
- 48 US Applications Filed
- 725 Total Citation Count
- Jul 30, 2024 Most Recent Filing
- Mar 20, 2007 Earliest Filing
Work History
| Patent Owner | Applications Filed | Year |
|---|---|---|
| TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD. | 5
3 8 8 17 12 4 2 1 | 2007
2010 2011 2012 2013 2014 2015 2016 2017 |
Inventor Addresses
| Address | Duration |
|---|---|
| Hsin-Chu City, TW | Nov 15, 07 - Nov 15, 07 |
| Hsin-Chu, TW | Oct 19, 10 - Apr 09, 13 |
| Hsin-chu, TW | Jan 01, 09 - Jan 01, 09 |
| Hsinchu City, TW | Nov 15, 07 - Nov 15, 07 |
| Hsinchu, TW | Mar 11, 21 - Nov 21, 24 |
| Taipei City, TW | Mar 01, 12 - Nov 21, 24 |
| Taipei, TW | Aug 28, 12 - Nov 05, 24 |
Technology Profile
| Technology | Matters | |
|---|---|---|
| G01R: | MEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES | 1 |
| G03C: | PHOTOSENSITIVE MATERIALS FOR PHOTOGRAPHIC PURPOSES | 1 |
| G03F: | PHOTOMECHANICAL PRODUCTION OF TEXTURED OR PATTERNED SURFACES, e.g. FOR PRINTING, FOR PROCESSING OF SEMICONDUCTOR DEVICES; MATERIALS THEREFOR; ORIGINALS THEREFOR; APPARATUS SPECIALLY ADAPTED THEREFOR | 11 |
Patents / Publication
| Patents / Publication # | Year of Publication / Issued | Title | Citations |
|---|---|---|---|
| 2024/0386,181 | 2024 | INTEGRATED CIRCUIT LAYOUT GENERATION METHOD AND SYSTEM | 1 |
| 2024/0386,178 | 2024 | METHOD OF MANUFACTURING SEMICONDUCTOR DEVICE AND SYSTEM FOR SAME | 0 |
| 12135930 | 2024 | Integrated circuit layout generation method and system | 0 |
| 12093629 | 2024 | Method of manufacturing semiconductor device and system for same | 0 |
| 2024/0160,828 | 2024 | INTEGRATED CIRCUIT LAYOUT GENERATION METHOD | 0 |
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