Dongbing Shao
Inventor
Stats
- 11 US patents issued
- 69 US Applications filed
- most recent filing
This is official USPTO record data
Details
- 11 US Patents Issued
- 69 US Applications Filed
- 161 Total Citation Count
- Aug 26, 2024 Most Recent Filing
- Oct 28, 2010 Earliest Filing
Work History
| Patent Owner | Applications Filed | Year |
|---|---|---|
| INTERNATIONAL BUSINESS MACHINES CORPORATION | 2
4 3 4 1 | 2011
2014 2015 2016 2017 |
| GLOBALFOUNDRIES INC. | 2
2 2 2 | 2010
2011 2015 2016 |
Inventor Addresses
| Address | Duration |
|---|---|
| Briarcliff Manor, NY, US | Apr 15, 21 - Dec 19, 24 |
| WAPPINGERS FALLS, NY, US | Mar 07, 19 - Sep 26, 19 |
| Wappinger Falls, NY, US | Aug 27, 19 - Aug 27, 19 |
| Wappingers Falls, NY, US | May 03, 12 - Aug 01, 24 |
| Wappingers Falls,, NY, US | Feb 27, 20 - Feb 27, 20 |
| Wappingers, NY, US | Aug 10, 17 - Feb 20, 18 |
Technology Profile
| Technology | Matters | |
|---|---|---|
| B82Y: | SPECIFIC USES OR APPLICATIONS OF NANO-STRUCTURES; MEASUREMENT OR ANALYSIS OF NANO-STRUCTURES; MANUFACTURE OR TREATMENT OF NANO-STRUCTURES | 1 |
| G01B: | MEASURING LENGTH, THICKNESS OR SIMILAR LINEAR DIMENSIONS; MEASURING ANGLES; MEASURING AREAS; MEASURING IRREGULARITIES OF SURFACES OR CONTOURS | 1 |
| G03F: | PHOTOMECHANICAL PRODUCTION OF TEXTURED OR PATTERNED SURFACES, e.g. FOR PRINTING, FOR PROCESSING OF SEMICONDUCTOR DEVICES; MATERIALS THEREFOR; ORIGINALS THEREFOR; APPARATUS SPECIALLY ADAPTED THEREFOR | 12 |
Patents / Publication
| Patents / Publication # | Year of Publication / Issued | Title | Citations |
|---|---|---|---|
| 2024/0421,113 | 2024 | UNIFORM CHIP GAPS VIA INJECTION-MOLDED SOLDER PILLARS | 0 |
| 12107065 | 2024 | Uniform chip gaps via injection-molded solder pillars | 0 |
| 2024/0258,113 | 2024 | TWO-COLOR SELF-ALIGNED DOUBLE PATTERNING (SADP) TO YIELD STATIC RANDOM ACCESS MEMORY (SRAM) AND DENSE LOGIC | 0 |
| 12039402 | 2024 | Color-map method to eliminate qubit frequency crowding in a quantum computing chip | 0 |
| 2024/0220,697 | 2024 | AUTOMATED DESIGN-TO-LITHOGRAPHY AND DESIGN CHECKING FOR STITCHED INTEGRATED CIRCUIT DESIGN | 0 |
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