Aseem Sayal
Inventor
Stats
- 0 US patents issued
- 12 US Applications filed
- most recent filing
This is official USPTO record data
Details
- 0 US Patents Issued
- 12 US Applications Filed
- 11 Total Citation Count
- Sep 1, 2024 Most Recent Filing
- Mar 21, 2017 Earliest Filing
Work History
No Work History Available.Inventor Addresses
| Address | Duration |
|---|---|
| Austin, TX, US | May 09, 19 - Dec 26, 24 |
Technology Profile
| Technology | Matters | |
|---|---|---|
| B81C: | PROCESSES OR APPARATUS SPECIALLY ADAPTED FOR THE MANUFACTURE OR TREATMENT OF MICRO-STRUCTURAL DEVICES OR SYSTEMS | 3 |
| G06F: | ELECTRIC DIGITAL DATA PROCESSING | 8 |
| G09B: | EDUCATIONAL OR DEMONSTRATION APPLIANCES; APPLIANCES FOR TEACHING, OR COMMUNICATING WITH, THE BLIND, DEAF OR MUTE; MODELS; PLANETARIA; GLOBES; MAPS; DIAGRAMS | 2 |
Patents / Publication
| Patents / Publication # | Year of Publication / Issued | Title | Citations |
|---|---|---|---|
| 2024/0429,099 | 2024 | NANOSCALE-ALIGNED THREE-DIMENSIONAL STACKED INTEGRATED CIRCUIT | 0 |
| 2024/0332,056 | 2024 | HETEROGENEOUS INTEGRATION OF COMPONENTS ONTO COMPACT DEVICES USING MOIRÉ BASED METROLOGY AND VACUUM BASED PICK-AND-PLACE | 0 |
| 12094775 | 2024 | Nanoscale-aligned three-dimensional stacked integrated circuit | 0 |
| 12079557 | 2024 | Nanofabrication and design techniques for 3D ICs and configurable ASICs | 0 |
| 12009247 | 2024 | Heterogeneous integration of components onto compact devices using moiré based metrology and vacuum based pick-and-place | 0 |
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