Sharmin Sadoughi
Inventor
Stats
- 12 US patents issued
- 12 US Applications filed
- most recent filing
This is official USPTO record data
Details
- 12 US Patents Issued
- 12 US Applications Filed
- 100 Total Citation Count
- Sep 9, 2011 Most Recent Filing
- Jun 30, 1997 Earliest Filing
Work History
| Patent Owner | Applications Filed | Year |
|---|---|---|
| XILINX, INC. | 3
4 | 2009
2011 |
| GASONICS INTERNATIONAL CORPORATION | 1
| 1997
|
| MONTEREY RESEARCH, LLC | 1
1 2 1 | 1997
2002 2004 2007 |
| CYPRESS SEMICONDUCTOR CORPORATION | 1
2 | 1997
2001 |
Inventor Addresses
| Address | Duration |
|---|---|
| Cupertino, CA | Mar 07, 00 - Jan 11, 05 |
| Menlo Park, CA | Aug 10, 04 - Aug 14, 07 |
| Menlo Park, CA, US | Dec 08, 09 - Feb 18, 14 |
Technology Profile
| Technology | Matters | |
|---|---|---|
| G01R: | MEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES | 1 |
| G06F: | ELECTRIC DIGITAL DATA PROCESSING | 2 |
| H01L: | SEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR | 10 |
Patents / Publication
| Patents / Publication # | Year of Publication / Issued | Title | Citations |
|---|---|---|---|
| 8653844 | 2014 | Calibrating device performance within an integrated circuit | 4 |
| 8302064 | 2012 | Method of product performance improvement by selective feature sizing of semiconductor devices | 4 |
| 2012/0229,203 | 2012 | CALIBRATING DEVICE PERFORMANCE WITHIN AN INTEGRATED CIRCUIT | 4 |
| 8183105 | 2012 | Integrated circuit device with stress reduction layer | 1 |
| 2012/0007,188 | 2012 | INTEGRATED CIRCUIT DEVICE WITH STRESS REDUCTION LAYER | 1 |
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