Rahul M Rao
Inventor
Stats
- 26 US patents issued
- 51 US Applications filed
- most recent filing
This is official USPTO record data
Details
- 26 US Patents Issued
- 51 US Applications Filed
- 262 Total Citation Count
- Jul 24, 2023 Most Recent Filing
- Dec 12, 2002 Earliest Filing
Work History
| Patent Owner | Applications Filed | Year |
|---|---|---|
| INTERNATIONAL BUSINESS MACHINES CORPORATION | 2
2 1 4 2 1 4 8 4 | 2002
2007 2010 2011 2012 2014 2015 2016 2017 |
| GLOBALFOUNDRIES INC. | 2
3 6 8 2 2 7 1 | 2004
2006 2007 2008 2009 2011 2012 2015 |
Inventor Addresses
| Address | Duration |
|---|---|
| Ann Arbor, MI | Sep 14, 04 - Aug 08, 06 |
| Ann Arbor, MI, US | Jun 17, 04 - Apr 20, 06 |
| Austin, TX, US | Jun 16, 09 - Jun 23, 15 |
| BANGALORE, IN | Oct 03, 24 - Jan 30, 25 |
| Bangalore, IN | Mar 08, 16 - Mar 25, 25 |
| Elmsford, NY | Mar 20, 08 - Dec 25, 08 |
| Elmsford, NY, US | Jul 31, 08 - Sep 03, 13 |
Technology Profile
| Technology | Matters | |
|---|---|---|
| G01R: | MEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES | 8 |
| G06F: | ELECTRIC DIGITAL DATA PROCESSING | 35 |
| G06G: | ANALOGUE COMPUTERS | 2 |
Patents / Publication
| Patents / Publication # | Year of Publication / Issued | Title | Citations |
|---|---|---|---|
| 12261165 | 2025 | Electronic circuits including hybrid voltage threshold logical entities | 0 |
| 2025/0036,188 | 2025 | POWER REDUCTION BY REMOVAL OF REDUNDANCY IN CLOCK PATHWAYS OF VLSI CIRCUITS | 0 |
| 2025/0005,251 | 2025 | EQUIVALENT WIRE CODES FOR ROUTING NETS IN AN INTEGRATED CIRCUIT DESIGN | 0 |
| 2024/0386,175 | 2024 | TIMING ANALYSIS FOR NON-SCAN LATCHES | 0 |
| 2024/0330,554 | 2024 | SCAN CHAIN OPTIMIZATION UTILIZING CONSTRAINED SINGLE LINKAGE CLUSTERING | 0 |
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