Vikas Rana
Inventor
Stats
- 13 US patents issued
- 59 US Applications filed
- most recent filing
This is official USPTO record data
Details
- 13 US Patents Issued
- 59 US Applications Filed
- 126 Total Citation Count
- Aug 16, 2024 Most Recent Filing
- Dec 24, 2008 Earliest Filing
Work History
| Patent Owner | Applications Filed | Year |
|---|---|---|
| STMICROELECTRONICS S.R.L. | 2
1 4 1 1 | 2013
2014 2015 2016 2017 |
| STMICROELECTRONICS INTERNATIONAL N.V. | 2
2 2 5 6 2 1 | 2010
2011 2013 2014 2015 2016 2017 |
| STMICROELECTRONICS PVT. LTD. | 2
1 | 2008
2009 |
Inventor Addresses
| Address | Duration |
|---|---|
| Greater Noida, IN | Apr 05, 11 - Apr 05, 11 |
| Juelich, DE | Apr 18, 19 - Apr 18, 19 |
| NOIDA, IN | Mar 03, 16 - Dec 02, 21 |
| Noida, IN | Dec 08, 11 - Feb 13, 25 |
| Noide, IN | Nov 25, 21 - Oct 18, 22 |
| Patiala, IN | Aug 23, 18 - May 05, 20 |
| Pehowa (KKR), IN | Jul 19, 12 - Jul 19, 12 |
| Pehowa, IN | Jun 24, 10 - Aug 29, 24 |
Technology Profile
| Technology | Matters | |
|---|---|---|
| A61K: | PREPARATIONS FOR MEDICAL, DENTAL, OR TOILET PURPOSES | 1 |
| G05F: | SYSTEMS FOR REGULATING ELECTRIC OR MAGNETIC VARIABLES | 6 |
| G06F: | ELECTRIC DIGITAL DATA PROCESSING | 4 |
Patents / Publication
| Patents / Publication # | Year of Publication / Issued | Title | Citations |
|---|---|---|---|
| 2025/0054,552 | 2025 | DEVICE AND METHOD TO GENERATE BIAS VOLTAGES IN NON-VOLATILE MEMORY | 0 |
| 2025/0029,664 | 2025 | CIRCUIT AND METHOD FOR ON-CHIP LEAKAGE DETECTION AND COMPENSATION FOR MEMORIES | 0 |
| 12148473 | 2024 | Non-volatile memory cell with single poly, floating gate extending over two wells | 0 |
| 2024/0312,495 | 2024 | MEMORY CIRCUIT ARRANGEMENT FOR ACCURATE AND SECURE READ | 0 |
| 12094542 | 2024 | Device and method to generate bias voltages in non-volatile memory | 0 |
We are sorry but your current selection exceeds the maximum number of portfolios (0) for this membership level.
>
Upgrade to our Level for up to -1 portfolios!.