Siddharth Rajan
Inventor
Stats
- 6 US patents issued
- 20 US Applications filed
- most recent filing
This is official USPTO record data
Details
- 6 US Patents Issued
- 20 US Applications Filed
- 255 Total Citation Count
- Sep 6, 2024 Most Recent Filing
- Sep 29, 2005 Earliest Filing
Work History
| Patent Owner | Applications Filed | Year |
|---|---|---|
| THE OHIO STATE UNIVERSITY RESEARCH FOUNDATION | 2
| 2011
|
| OHIO STATE INNOVATION FOUNDATION | 2
| 2016
|
| GENERAL ELECTRIC COMPANY | 3
2 | 2007
2012 |
| THE REGENTS OF THE UNIVERSITY OF CALIFORNIA | 2
2 3 | 2005
2006 2008 |
Inventor Addresses
| Address | Duration |
|---|---|
| Columbus, OH, US | Aug 15, 13 - Mar 13, 25 |
| Goleta, CA | Oct 19, 06 - Oct 02, 08 |
| Goleta, CA, US | Apr 02, 09 - Apr 15, 14 |
Technology Profile
| Technology | Matters | |
|---|---|---|
| B82Y: | SPECIFIC USES OR APPLICATIONS OF NANO-STRUCTURES; MEASUREMENT OR ANALYSIS OF NANO-STRUCTURES; MANUFACTURE OR TREATMENT OF NANO-STRUCTURES | 1 |
| H01L: | SEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR | 20 |
Patents / Publication
| Patents / Publication # | Year of Publication / Issued | Title | Citations |
|---|---|---|---|
| 2025/0087,479 | 2025 | ETCHING METHODS AND PATTERNED SUBSTRATES MADE USING SAID METHODS | 0 |
| 2024/0249,954 | 2024 | IN SITU DAMAGE FREE ETCHING OF Ga2O3 USING Ga FLUX FOR FABRICATING HIGH ASPECT RATIO 3D STRUCTURES | 0 |
| 2024/0014,285 | 2024 | SEMICONDUCTOR DEVICES WITH A COMPOSITIONALLY GRADED LAYER, AND METHODS OF MAKING AND USE THEREOF | 0 |
| 11848359 | 2023 | Method of forming lateral pn junctions in III-nitrides using p-type and n-type co-doping and selective p-type activation and deactivation | 0 |
| 11848389 | 2023 | Low turn on and high breakdown voltage lateral diode | 0 |
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