Thierry Poiroux
Inventor
Stats
- 20 US patents issued
- 22 US Applications filed
- most recent filing
This is official USPTO record data
Details
- 20 US Patents Issued
- 22 US Applications Filed
- 174 Total Citation Count
- Nov 30, 2017 Most Recent Filing
- Sep 26, 2003 Earliest Filing
Work History
| Patent Owner | Applications Filed | Year |
|---|---|---|
| COMMISSARIAT A L'ENERGIE ATOMIQUE | 1
2 6 8 2 2 | 2003
2005 2006 2007 2008 2009 |
| COMMISSARIAT A L'ENERGIE ATOMIQUE ET AUX ENERGIES ALTERNATIVES | 6
6 4 2 | 2010
2011 2012 2014 |
| STMicroelectronics S.A. | 1
4 | 2003
2006 |
| STMICROELECTRONICS (CROLLES 2) SAS | 4
| 2011
|
| STMICROELECTRONICS (GRENOBLE 2) SAS | 2
| 2011
|
Inventor Addresses
| Address | Duration |
|---|---|
| Grenoble, FR | Jun 21, 12 - Jun 21, 12 |
| VOIRON, FR | Jun 07, 18 - Jun 07, 18 |
| Voiron, FR | Jun 24, 10 - Feb 09, 21 |
| Voreppe, FR | Aug 17, 04 - Mar 19, 13 |
Technology Profile
| Technology | Matters | |
|---|---|---|
| B82Y: | SPECIFIC USES OR APPLICATIONS OF NANO-STRUCTURES; MEASUREMENT OR ANALYSIS OF NANO-STRUCTURES; MANUFACTURE OR TREATMENT OF NANO-STRUCTURES | 1 |
| G01B: | MEASURING LENGTH, THICKNESS OR SIMILAR LINEAR DIMENSIONS; MEASURING ANGLES; MEASURING AREAS; MEASURING IRREGULARITIES OF SURFACES OR CONTOURS | 1 |
| G01N: | INVESTIGATING OR ANALYSING MATERIALS BY DETERMINING THEIR CHEMICAL OR PHYSICAL PROPERTIES | 1 |
Patents / Publication
| Patents / Publication # | Year of Publication / Issued | Title | Citations |
|---|---|---|---|
| 10914703 | 2021 | Computer implemented method for determining intrinsic parameter in a stacked nanowires MOSFET | 2 |
| 2018/0156,749 | 2018 | COMPUTER IMPLEMENTED METHOD FOR DETERMINING INTRINSIC PARAMETER IN A STACKED NANOWIRES MOSFET | 12 |
| 2018/0097,014 | 2018 | FDSOI-TYPE FIELD-EFFECT TRANSISTORS | 0 |
| 2016/0019,327 | 2016 | COMPUTER IMPLEMENTED METHOD FOR CALCULATING A CHARGE DENSITY AT A GATE INTERFACE OF A DOUBLE GATE TRANSISTOR | 0 |
| 9235668 | 2016 | Computer implemented method for calculating a charge density at a gate interface of a double gate transistor | 1 |
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