Suraj K Patil
Inventor
Stats
- 14 US patents issued
- 24 US Applications filed
- most recent filing
This is official USPTO record data
Details
- 14 US Patents Issued
- 24 US Applications Filed
- 170 Total Citation Count
- May 24, 2018 Most Recent Filing
- Aug 14, 2009 Earliest Filing
Work History
| Patent Owner | Applications Filed | Year |
|---|---|---|
| BOARD OF REGENTS, THE UNIVERSITY OF TEXAS SYSTEM | 2
2 | 2009
2013 |
| GLOBALFOUNDRIES INC. | 2
4 12 5 1 | 2013
2014 2015 2016 2017 |
Inventor Addresses
| Address | Duration |
|---|---|
| Arlington, TX, US | Apr 29, 10 - Jul 23, 13 |
| Austin, TX, US | Sep 19, 19 - Feb 25, 20 |
| Ballston Lake, NY, US | Apr 03, 14 - May 02, 19 |
| Chino Hills, CA, US | Mar 19, 19 - Mar 28, 19 |
| Malta, NY, US | Jul 04, 17 - Jul 04, 17 |
Technology Profile
| Technology | Matters | |
|---|---|---|
| G01L: | MEASURING FORCE, STRESS, TORQUE, WORK, MECHANICAL POWER, MECHANICAL EFFICIENCY, OR FLUID PRESSURE | 1 |
| G03F: | PHOTOMECHANICAL PRODUCTION OF TEXTURED OR PATTERNED SURFACES, e.g. FOR PRINTING, FOR PROCESSING OF SEMICONDUCTOR DEVICES; MATERIALS THEREFOR; ORIGINALS THEREFOR; APPARATUS SPECIALLY ADAPTED THEREFOR | 1 |
| G11C: | STATIC STORES | 2 |
Patents / Publication
| Patents / Publication # | Year of Publication / Issued | Title | Citations |
|---|---|---|---|
| 10573552 | 2020 | Semiconductor device and method of fabricating the same | 3 |
| 2019/0287,849 | 2019 | SEMICONDUCTOR DEVICE AND METHOD OF FABRICATING THE SAME | 3 |
| 2019/0131,424 | 2019 | METHODS FOR FORMING IC STRUCTURE HAVING RECESSED GATE SPACERS AND RELATED IC STRUCTURES | 1 |
| 2019/0096,679 | 2019 | GATE STACK PROCESSES AND STRUCTURES | 10 |
| 10236358 | 2019 | Integration of gate structures and spacers with air gaps | 3 |
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