Paul Packan
Inventor
Stats
- 8 US patents issued
- 17 US Applications filed
- most recent filing
This is official USPTO record data
Details
- 8 US Patents Issued
- 17 US Applications Filed
- 454 Total Citation Count
- Sep 29, 2023 Most Recent Filing
- Dec 31, 1996 Earliest Filing
Work History
| Patent Owner | Applications Filed | Year |
|---|---|---|
| INTEL CORPORATION | 1
1 1 1 1 2 1 1 | 1996
1998 1999 2004 2006 2008 2010 2017 |
Inventor Addresses
| Address | Duration |
|---|---|
| Beaverton, OR | Jun 01, 99 - Oct 14, 08 |
| Beaverton, OR, US | Jan 08, 09 - Mar 01, 22 |
| Hillsboro, OR, US | Oct 05, 23 - Apr 03, 25 |
Technology Profile
| Technology | Matters | |
|---|---|---|
| H01L: | SEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR | 16 |
| H02H: | EMERGENCY PROTECTIVE CIRCUIT ARRANGEMENTS | 1 |
| H03B: | GENERATION OF OSCILLATIONS, DIRECTLY OR BY FREQUENCY-CHANGING, BY CIRCUITS EMPLOYING ACTIVE ELEMENTS WHICH OPERATE IN A NON-SWITCHING MANNER; GENERATION OF NOISE BY SUCH CIRCUITS | 1 |
Patents / Publication
| Patents / Publication # | Year of Publication / Issued | Title | Citations |
|---|---|---|---|
| 2025/0113,595 | 2025 | MULTIPLE VOLTAGE THRESHOLD INTEGRATED CIRCUIT STRUCTURE WITH LOCAL LAYOUT EFFECT TUNING | 0 |
| 2025/0112,120 | 2025 | INTEGRATED CIRCUIT STRUCTURE WITH DEEP VIA BAR WIDTH TUNING | 0 |
| 2025/0107,175 | 2025 | INTEGRATED CIRCUIT STRUCTURES HAVING REDUCED LOCAL LAYOUT EFFECTS | 0 |
| 2025/0006,734 | 2025 | PERFORMANCE OPTIMIZATION OF TRANSISTORS SHARING CHANNEL STRUCTURES OF VARYING WIDTH | 0 |
| 2024/0321,859 | 2024 | INTEGRATED CIRCUIT DEVICE WITH PERFORMANCE-ENHANCING LAYOUT | 0 |
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