GERALD S PASDAST
Inventor
Stats
- 2 US patents issued
- 28 US Applications filed
- most recent filing
This is official USPTO record data
Details
- 2 US Patents Issued
- 28 US Applications Filed
- 184 Total Citation Count
- Jul 2, 2024 Most Recent Filing
- Dec 26, 2013 Earliest Filing
Work History
| Patent Owner | Applications Filed | Year |
|---|---|---|
| INTEL CORPORATION | 1
2 1 1 | 2013
2014 2015 2017 |
Inventor Addresses
| Address | Duration |
|---|---|
| San Jose, CA, US | Jun 30, 16 - Apr 03, 25 |
| San Jose, US | Jan 25, 24 - Jan 25, 24 |
Technology Profile
| Technology | Matters | |
|---|---|---|
| G01R: | MEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES | 3 |
| G06F: | ELECTRIC DIGITAL DATA PROCESSING | 9 |
| H01L: | SEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR | 17 |
Patents / Publication
| Patents / Publication # | Year of Publication / Issued | Title | Citations |
|---|---|---|---|
| 2025/0112,660 | 2025 | BIDIRECTIONAL LINK WITH HYBRID SUPPRESSION CIRCUIT | 0 |
| 12266682 | 2025 | Capacitors and resistors at direct bonding interfaces in microelectronic assemblies | 0 |
| 2024/0355,768 | 2024 | MICROELECTRONIC ASSEMBLIES WITH INDUCTORS IN DIRECT BONDING REGIONS | 0 |
| 12117960 | 2024 | Approximate data bus inversion technique for latency sensitive applications | 1 |
| 12107060 | 2024 | Microelectronic assemblies with inductors in direct bonding regions | 1 |
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