Victor Moroz
Inventor
Stats
- 90 US patents issued
- 168 US Applications filed
- most recent filing
This is official USPTO record data
Details
- 90 US Patents Issued
- 168 US Applications Filed
- 2079 Total Citation Count
- Jul 31, 2024 Most Recent Filing
- Aug 30, 2004 Earliest Filing
Work History
Patent Owner | Applications Filed | Year |
---|---|---|
SYNOPSYS, INC. | 2
7 11 19 4 30 2 18 15 16 43 18 10 7 | 2004
2005 2006 2007 2008 2009 2010 2011 2012 2013 2014 2015 2016 2017 |
APPLIED MATERIALS, INC. | 2
4 | 2005
2008 |
Synopsy, Inc. | 1
| 2011
|
Inventor Addresses
Address | Duration |
---|---|
Mountain View, CA, US | Aug 12, 21 - Dec 06, 22 |
SARATOGA, CA | Dec 27, 07 - Dec 27, 07 |
SARATOGA, CA, US | Feb 04, 10 - Nov 21, 19 |
San Jose, CA | - |
San Jose, CA, US | May 10, 11 - Jan 08, 13 |
Saratoga, CA | Mar 13, 07 - Mar 06, 14 |
Saratoga, CA, US | Dec 29, 05 - Nov 28, 24 |
Technology Profile
Technology | Matters | |
---|---|---|
B05C: | APPARATUS FOR APPLYING LIQUIDS OR OTHER FLUENT MATERIALS TO SURFACES, IN GENERAL | 1 |
B82Y: | SPECIFIC USES OR APPLICATIONS OF NANO-STRUCTURES; MEASUREMENT OR ANALYSIS OF NANO-STRUCTURES; MANUFACTURE OR TREATMENT OF NANO-STRUCTURES | 3 |
C23F: | NON-MECHANICAL REMOVAL OF METALLIC MATERIAL FROM SURFACES | 1 |
Patents / Publication
Patents / Publication # | Year of Publication / Issued | Title | Citations |
---|---|---|---|
2024/0395,630 | 2024 | SELF-LIMITING MANUFACTURING TECHNIQUES TO PREVENT ELECTRICAL SHORTS IN A COMPLEMENTARY FIELD EFFECT TRANSISTOR (CFET) | 0 |
12086523 | 2024 | Adaptive row patterns for custom-tiled placement fabrics for mixed height cell libraries | 0 |
12080608 | 2024 | Self-limiting manufacturing techniques to prevent electrical shorts in a complementary field effect transistor (CFET) | 0 |
2024/0258,206 | 2024 | Power Routing for 2.5D or 3D Integrated Circuits Including a Buried Power Rail and Interposer with Power Delivery Network | 0 |
12041858 | 2024 | Josephson junction structures | 0 |
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