Robert G Mathews
Inventor
Stats
- 7 US patents issued
- 7 US Applications filed
- most recent filing
This is official USPTO record data
Details
- 7 US Patents Issued
- 7 US Applications Filed
- 429 Total Citation Count
- Jan 24, 2002 Most Recent Filing
- Sep 25, 1997 Earliest Filing
Work History
| Patent Owner | Applications Filed | Year |
|---|---|---|
| APACHE DESIGN, INC. | 1
5 2 | 1997
1999 2002 |
| FREQUENCY TECHNOLOGY, INC. | 1
2 | 1997
1999 |
Inventor Addresses
| Address | Duration |
|---|---|
| Los Altos, CA | May 02, 00 - Nov 04, 03 |
| Los Altos, CA, US | Aug 01, 02 - Aug 01, 02 |
Technology Profile
| Technology | Matters | |
|---|---|---|
| G01L: | MEASURING FORCE, STRESS, TORQUE, WORK, MECHANICAL POWER, MECHANICAL EFFICIENCY, OR FLUID PRESSURE | 2 |
| G01R: | MEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES | 1 |
| G06F: | ELECTRIC DIGITAL DATA PROCESSING | 3 |
Patents / Publication
| Patents / Publication # | Year of Publication / Issued | Title | Citations |
|---|---|---|---|
| 6643831 | 2003 | Method and system for extraction of parasitic interconnect impedance including inductance | 236 |
| 2002/0104,063 | 2002 | Method and system for extraction of parasitic interconnect impedance including inductance | 12 |
| 6403389 | 2002 | Method for determining on-chip sheet resistivity | 23 |
| 6381730 | 2002 | Method and system for extraction of parasitic interconnect impedance including inductance | 57 |
| 6312963 | 2001 | Methods for determining on-chip interconnect process parameters | 25 |
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