Yasukazu Mase
Inventor
Stats
- 19 US patents issued
- 19 US Applications filed
- most recent filing
This is official USPTO record data
Details
- 19 US Patents Issued
- 19 US Applications Filed
- 526 Total Citation Count
- Jun 4, 1998 Most Recent Filing
- Jul 24, 1984 Earliest Filing
Work History
Patent Owner | Applications Filed | Year |
---|---|---|
KABUSHIKI KAISHA TOSHIBA | 1
1 1 2 2 4 2 2 2 1 1 | 1984
1985 1986 1988 1989 1990 1991 1993 1995 1997 1998 |
CELLTECH THERAPEUTICS LIMITED | 1
| 1995
|
NUFLARE TECHNOLOGY, INC. | 1
| 1995
|
MATSUSHITA ELECTRIC WORKS, LTD. | 1
| 1990
|
Inventor Addresses
Address | Duration |
---|---|
Fujisawa, JP | Aug 28, 90 - Jun 04, 96 |
Fuyisawa, JP | Feb 20, 01 - Feb 20, 01 |
Tokyo, JP | Sep 23, 86 - Dec 08, 92 |
Yokohama, JP | Aug 12, 97 - Jan 18, 00 |
Technology Profile
Technology | Matters | |
---|---|---|
B08B: | CLEANING IN GENERAL; PREVENTION OF FOULING IN GENERAL | 1 |
B24B: | MACHINES, DEVICES, OR PROCESSES FOR GRINDING OR POLISHING | 1 |
B29C: | SHAPING OR JOINING OF PLASTICS; SHAPING OF SUBSTANCES IN A PLASTIC STATE, IN GENERAL; AFTER- TREATMENT OF THE SHAPED PRODUCTS, e.g. REPAIRING | 1 |
Patents / Publication
Patents / Publication # | Year of Publication / Issued | Title | Citations |
---|---|---|---|
RE37059 | 2001 | Wiring pattern of semiconductor integrated circuit device | 0 |
6015754 | 2000 | Chemical mechanical polishing apparatus and method | 12 |
5655954 | 1997 | Polishing apparatus | 104 |
5523627 | 1996 | Wiring pattern of semiconductor integrated circuit device | 5 |
5411916 | 1995 | Method for patterning wirings of semiconductor integrated circuit device | 2 |
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