Dalhee Lee
Inventor
Stats
- 0 US patents issued
- 15 US Applications filed
- most recent filing
This is official USPTO record data
Details
- 0 US Patents Issued
- 15 US Applications Filed
- 33 Total Citation Count
- Mar 6, 2024 Most Recent Filing
- Oct 4, 2016 Earliest Filing
Work History
| Patent Owner | Applications Filed | Year |
|---|---|---|
| SAMSUNG ELECTRONICS CO., LTD. | 1
1 | 2016
2017 |
Inventor Addresses
| Address | Duration |
|---|---|
| Seoul, KR | Apr 27, 17 - Jan 02, 24 |
| Suwon-si, KR | Feb 22, 24 - Mar 11, 25 |
Technology Profile
| Technology | Matters | |
|---|---|---|
| G01R: | MEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES | 3 |
| G06F: | ELECTRIC DIGITAL DATA PROCESSING | 2 |
| G11C: | STATIC STORES | 1 |
Patents / Publication
| Patents / Publication # | Year of Publication / Issued | Title | Citations |
|---|---|---|---|
| 12249993 | 2025 | Asymmetric NAND gate circuit, clock gating cell and integrated circuit including the same | 0 |
| 2024/0429,168 | 2024 | INTEGRATED CIRCUIT INCLUDING BACKSIDE WIRING AND METHOD OF DESIGNING THE INTEGRATED CIRCUIT | 0 |
| 12044733 | 2024 | Flip-flops and scan chain circuits including the same | 0 |
| 2024/0235,533 | 2024 | ASYMMETRIC NAND GATE CIRCUIT, CLOCK GATING CELL AND INTEGRATED CIRCUIT INCLUDING THE SAME | 0 |
| 2024/0137,012 | 2024 | ASYMMETRIC NAND GATE CIRCUIT, CLOCK GATING CELL AND INTEGRATED CIRCUIT INCLUDING THE SAME | 0 |
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