Stephan Lassig
Inventor
Stats
- 3 US patents issued
- 5 US Applications filed
- most recent filing
This is official USPTO record data
Details
- 3 US Patents Issued
- 5 US Applications Filed
- 62 Total Citation Count
- Apr 20, 2016 Most Recent Filing
- Oct 5, 2001 Earliest Filing
Work History
Patent Owner | Applications Filed | Year |
---|---|---|
LAM RESEARCH CORPORATION | 1
1 1 2 2 | 2001
2002 2004 2008 2016 |
NOVELLUS SYSTEMS, INC. | 1
| 2002
|
Inventor Addresses
Address | Duration |
---|---|
Danville, CA | Apr 05, 05 - Apr 05, 05 |
Danville, CA, US | Feb 26, 04 - Jan 09, 18 |
Technology Profile
Technology | Matters | |
---|---|---|
B44C: | PRODUCING DECORATIVE EFFECTS | 1 |
C03C: | CHEMICAL COMPOSITION OF GLASSES, GLAZES, OR VITREOUS ENAMELS; SURFACE TREATMENT OF GLASS; SURFACE TREATMENT OF FIBRES OR FILAMENTS FROM GLASS, MINERALS OR SLAGS; JOINING GLASS TO GLASS OR OTHER MATERIALS | 1 |
C23F: | NON-MECHANICAL REMOVAL OF METALLIC MATERIAL FROM SURFACES | 1 |
Patents / Publication
Patents / Publication # | Year of Publication / Issued | Title | Citations |
---|---|---|---|
9865472 | 2018 | Fabrication of a silicon structure and deep silicon etch with profile control | 3 |
2016/0233,102 | 2016 | FABRICATION OF A SILICON STRUCTURE AND DEEP SILICON ETCH WITH PROFILE CONTROL | 0 |
9330926 | 2016 | Fabrication of a silicon structure and deep silicon etch with profile control | 4 |
2009/0184,089 | 2009 | FABRICATION OF A SILICON STRUCTURE AND DEEP SILICON ETCH WITH PROFILE CONTROL | 22 |
6875699 | 2005 | Method for patterning multilevel interconnects | 4 |
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