Roza Kotlyar
Inventor
Stats
- 25 US patents issued
- 55 US Applications filed
- most recent filing
This is official USPTO record data
Details
- 25 US Patents Issued
- 55 US Applications Filed
- 800 Total Citation Count
- Oct 6, 2023 Most Recent Filing
- Apr 12, 2005 Earliest Filing
Work History
Patent Owner | Applications Filed | Year |
---|---|---|
INTEL CORPORATION | 1
2 4 7 9 7 4 6 2 | 2005
2009 2010 2012 2013 2014 2015 2016 2017 |
Inventor Addresses
Address | Duration |
---|---|
PORTLAND, OR, US | Sep 22, 16 - Sep 22, 16 |
Portand, OR, US | Jan 12, 17 - Jan 12, 17 |
Portland, OR | Oct 12, 06 - Oct 12, 06 |
Portland, OR, US | Jun 30, 11 - Feb 18, 25 |
Technology Profile
Technology | Matters | |
---|---|---|
B82Y: | SPECIFIC USES OR APPLICATIONS OF NANO-STRUCTURES; MEASUREMENT OR ANALYSIS OF NANO-STRUCTURES; MANUFACTURE OR TREATMENT OF NANO-STRUCTURES | 7 |
G06F: | ELECTRIC DIGITAL DATA PROCESSING | 1 |
G06N: | COMPUTER SYSTEMS BASED ON SPECIFIC COMPUTATIONAL MODELS | 8 |
Patents / Publication
Patents / Publication # | Year of Publication / Issued | Title | Citations |
---|---|---|---|
12230687 | 2025 | Lateral gate material arrangements for quantum dot devices | 0 |
2024/0354,613 | 2024 | METHOD AND APPARATUS FOR LOADING CLASSICAL DATA INTO QUANTUM COMPUTERS | 0 |
11922274 | 2024 | Quantum dot devices with side and center screening gates | 0 |
11677017 | 2023 | Quantum well stacks for quantum dot devices | 0 |
2023/0170,388 | 2023 | CMOS FINFET DEVICE HAVING STRAINED SIGE FINS AND A STRAINED SI CLADDING LAYER ON THE NMOS CHANNEL | 0 |
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