Vasan Karighattam
Inventor
Stats
- 4 US patents issued
- 5 US Applications filed
- most recent filing
This is official USPTO record data
Details
- 4 US Patents Issued
- 5 US Applications Filed
- 52 Total Citation Count
- Dec 8, 2014 Most Recent Filing
- Jun 29, 2004 Earliest Filing
Work History
| Patent Owner | Applications Filed | Year |
|---|---|---|
| INTEL CORPORATION | 2
1 2 | 2004
2006 2012 |
| OPEN-SILICON INC. | 1
| 2014
|
Inventor Addresses
| Address | Duration |
|---|---|
| Davis, CA | Oct 04, 07 - Oct 04, 07 |
| Davis, CA, US | Apr 28, 09 - Mar 01, 16 |
| Milpitas, CA, US | Jun 09, 16 - May 01, 18 |
Technology Profile
| Technology | Matters | |
|---|---|---|
| G01R: | MEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES | 2 |
| G06F: | ELECTRIC DIGITAL DATA PROCESSING | 2 |
| H04K: | SECRET COMMUNICATION; JAMMING OF COMMUNICATION | 1 |
Patents / Publication
| Patents / Publication # | Year of Publication / Issued | Title | Citations |
|---|---|---|---|
| 9960909 | 2018 | High speed and low power hashing system and method | 6 |
| 2016/0164,672 | 2016 | HIGH SPEED AND LOW POWER HASHING SYSTEM AND METHOD | 17 |
| 9274169 | 2016 | Asynchronous programmable JTAG-based interface to debug any system-on-chip states, power modes, resets, clocks, and complex digital logic | 2 |
| 2014/0181,605 | 2014 | ASYNCHRONOUS PROGRAMMABLE JTAG-BASED INTERFACE TO DEBUG ANY SYSTEM-ON-CHIP STATES, POWER MODES, RESETS, CLOCKS, AND COMPLEX DIGITAL LOGIC | 3 |
| 7583599 | 2009 | Transporting stream client signals via packet interface using GFP mapping | 8 |
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