Tomoyasu Kakegawa
Inventor
Stats
- 10 US patents issued
- 17 US Applications filed
- most recent filing
This is official USPTO record data
Details
- 10 US Patents Issued
- 17 US Applications Filed
- 191 Total Citation Count
- Sep 29, 2017 Most Recent Filing
- Jul 21, 2008 Earliest Filing
Work History
| Patent Owner | Applications Filed | Year |
|---|---|---|
| LONGITUDE SEMICONDUCTOR S.A.R.L. | 2
2 2 1 | 2008
2011 2012 2013 |
| SANDISK TECHNOLOGIES LLC | 8
4 | 2014
2015 |
| ELPIDA MEMORY, INC. | 1
2 | 2010
2012 |
| PS4 LUXCO S.A.R.L. | 2
1 | 2008
2013 |
Inventor Addresses
| Address | Duration |
|---|---|
| Mie, JP | Feb 04, 16 - Oct 11, 16 |
| Tokyo, JP | Jan 29, 09 - Jun 23, 15 |
| Yokkaichi, JP | Nov 03, 15 - Oct 30, 18 |
Technology Profile
| Technology | Matters | |
|---|---|---|
| B05D: | PROCESSES FOR APPLYING LIQUIDS OR OTHER FLUENT MATERIALS TO SURFACES, IN GENERAL | 1 |
| B23P: | OTHER WORKING OF METAL; COMBINED OPERATIONS; UNIVERSAL MACHINE TOOLS | 1 |
| G11C: | STATIC STORES | 1 |
Patents / Publication
| Patents / Publication # | Year of Publication / Issued | Title | Citations |
|---|---|---|---|
| 10115459 | 2018 | Multiple liner interconnects for three dimensional memory devices and method of making thereof | 23 |
| 9847249 | 2017 | Buried etch stop layer for damascene bit line formation | 3 |
| 9799527 | 2017 | Double trench isolation | 2 |
| 9768183 | 2017 | Source line formation and structure | 2 |
| 2017/0040,333 | 2017 | Contact Plug Constrained By Dielectric Portions | 0 |
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