Nikos Kaburlasos
Inventor
Stats
- 20 US patents issued
- 126 US Applications filed
- most recent filing
This is official USPTO record data
Details
- 20 US Patents Issued
- 126 US Applications Filed
- 674 Total Citation Count
- Dec 9, 2024 Most Recent Filing
- Feb 22, 2002 Earliest Filing
Work History
| Patent Owner | Applications Filed | Year |
|---|---|---|
| INTEL CORPORATION | 2
2 4 2 2 3 9 8 5 2 2 1 | 2002
2006 2007 2008 2009 2010 2011 2012 2013 2014 2015 2016 |
Inventor Addresses
| Address | Duration |
|---|---|
| 3300 Capital Center Dr. #149 | Jul 13, 10 - Jul 13, 10 |
| FOLSOM, CA, US | May 20, 21 - Nov 23, 23 |
| Folsom, CA, US | Mar 05, 20 - Apr 10, 25 |
| Lincoln, CA, US | Oct 01, 09 - Mar 06, 25 |
| Rancho Cordova, CA, US | Mar 19, 09 - Jul 03, 18 |
| Sacramento, CA | Mar 01, 05 - Mar 01, 05 |
| Sacramento, CA, US | Aug 28, 03 - Aug 28, 03 |
| San Francisco, CA | Jul 05, 07 - Jul 05, 07 |
| San Francisco, CA, US | Jan 13, 09 - Jan 13, 09 |
Technology Profile
| Technology | Matters | |
|---|---|---|
| G01R: | MEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES | 1 |
| G02B: | OPTICAL ELEMENTS, SYSTEMS, OR APPARATUS | 4 |
| G05F: | SYSTEMS FOR REGULATING ELECTRIC OR MAGNETIC VARIABLES | 2 |
Patents / Publication
| Patents / Publication # | Year of Publication / Issued | Title | Citations |
|---|---|---|---|
| 2025/0117,060 | 2025 | PROCESSOR POWER MANAGEMENT | 0 |
| 2025/0117,875 | 2025 | REDUCE POWER BY FRAME SKIPPING | 0 |
| 2025/0103,430 | 2025 | SYSTEMS AND METHODS FOR ERROR DETECTION AND CONTROL FOR EMBEDDED MEMORY AND COMPUTE ELEMENTS | 0 |
| 2025/0103,343 | 2025 | DATA LOCALITY ENHANCEMENT FOR GRAPHICS PROCESSING UNITS | 0 |
| 12253901 | 2025 | Systems and methods for stable and elevated idle-mode temperature for assembled semiconductor devices | 0 |
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