Christopher Jezewski
Inventor
Stats
- 3 US patents issued
- 29 US Applications filed
- most recent filing
This is official USPTO record data
Details
- 3 US Patents Issued
- 29 US Applications Filed
- 157 Total Citation Count
- May 17, 2024 Most Recent Filing
- Dec 27, 2011 Earliest Filing
Work History
| Patent Owner | Applications Filed | Year |
|---|---|---|
| INTEL CORPORATION | 1
4 1 | 2011
2013 2016 |
Inventor Addresses
| Address | Duration |
|---|---|
| Hillsboro, OR, US | Mar 06, 14 - Feb 05, 19 |
| Portland, OR, US | Jan 02, 20 - Jan 28, 25 |
Technology Profile
| Technology | Matters | |
|---|---|---|
| C23C: | COATING METALLIC MATERIAL; COATING MATERIAL WITH METALLIC MATERIAL; SURFACE TREATMENT OF METALLIC MATERIAL BY DIFFUSION INTO THE SURFACE, BY CHEMICAL CONVERSION OR SUBSTITUTION; COATING BY VACUUM EVAPORATION, BY SPUTTERING, BY ION IMPLANTATION OR BY CHEMICAL VAPOUR DEPOSITION, IN GENERAL | 1 |
| C25D: | PROCESSES FOR THE ELECTROLYTIC OR ELECTROPHORETIC PRODUCTION OF COATINGS; ELECTROFORMING | 1 |
| D03D: | WOVEN FABRICS; METHODS OF WEAVING; LOOMS | 3 |
Patents / Publication
| Patents / Publication # | Year of Publication / Issued | Title | Citations |
|---|---|---|---|
| 12211794 | 2025 | Integrated circuits and methods for forming thin film crystal layers | 0 |
| 12165917 | 2024 | Integrated circuit interconnect structures with ultra-thin metal chalcogenide barrier materials | 0 |
| 12107170 | 2024 | Transistor channel passivation with 2D crystalline material | 0 |
| 12107085 | 2024 | Interconnect techniques for electrically connecting source/drain regions of stacked transistors | 0 |
| 2024/0304,543 | 2024 | SUBTRACTIVELY PATTERNED INTERCONNECT STRUCTURES FOR INTEGRATED CIRCUITS | 0 |
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