Michael S Hsiao
Inventor
Stats
- 6 US patents issued
- 8 US Applications filed
- most recent filing
This is official USPTO record data
Details
- 6 US Patents Issued
- 8 US Applications Filed
- 161 Total Citation Count
- Feb 23, 2017 Most Recent Filing
- Dec 31, 1997 Earliest Filing
Work History
Patent Owner | Applications Filed | Year |
---|---|---|
Syntest Technologies, Inc. | 1
2 | 2009
2011 |
VIRGINIA POLYTECHNIC INSTITUTE AND STATE UNIVERSITY | 2
| 2005
|
NEC CORPORATION | 2
2 | 1997
2001 |
FUJITSU LIMITED | 2
| 2003
|
NEC USA, INC., C & C RESEARCH LABORATORIES | 1
| 1997
|
Inventor Addresses
Address | Duration |
---|---|
Blacksburg, VA | Jul 11, 06 - Apr 08, 08 |
Blacksburg, VA, US | Nov 25, 04 - Nov 24, 20 |
Highland Park, NJ | Nov 09, 99 - Nov 07, 00 |
Princeton, NJ | May 11, 04 - May 11, 04 |
Princeton, NJ, US | Sep 19, 02 - Sep 19, 02 |
Technology Profile
Technology | Matters | |
---|---|---|
A63F: | CARD, BOARD, OR ROULETTE GAMES; INDOOR GAMES USING SMALL MOVING PLAYING BODIES; GAMES NOT OTHERWISE PROVIDED FOR | 1 |
G01R: | MEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES | 6 |
G06F: | ELECTRIC DIGITAL DATA PROCESSING | 6 |
Patents / Publication
Patents / Publication # | Year of Publication / Issued | Title | Citations |
---|---|---|---|
10843080 | 2020 | Automated program synthesis from natural language for domain specific computing applications | 1 |
2017/0239,576 | 2017 | AUTOMATED PROGRAM SYNTHESIS FROM NATURAL LANGUAGE FOR DOMAIN SPECIFIC COMPUTING APPLICATIONS | 22 |
8522096 | 2013 | Method and apparatus for testing 3D integrated circuits | 29 |
2012/0110,402 | 2012 | METHOD AND APPARATUS FOR TESTING 3D INTEGRATED CIRCUITS | 15 |
2010/0138,709 | 2010 | METHOD AND APPARATUS FOR DELAY FAULT COVERAGE ENHANCEMENT | 4 |
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