Edward R Helder
Inventor
Stats
- 3 US patents issued
- 5 US Applications filed
- most recent filing
This is official USPTO record data
Details
- 3 US Patents Issued
- 5 US Applications Filed
- 102 Total Citation Count
- Oct 24, 2003 Most Recent Filing
- Jul 7, 1989 Earliest Filing
Work History
| Patent Owner | Applications Filed | Year |
|---|---|---|
| INTEL CORPORATION | 2
| 2003
|
| HEWLETT PACKARD ENTERPRISE DEVELOPMENT LP | 1
| 2000
|
| Hewlett-Packard Deveolopment Company, L,P, | 1
| 2003
|
| HEWLETT-PACKARD DEVELOPMENT COMPANY, L.P. | 1
1 | 1989
2003 |
Inventor Addresses
| Address | Duration |
|---|---|
| Freemont, CA | Apr 28, 05 - Apr 28, 05 |
| Fremont, CA | Jan 15, 91 - Jul 24, 07 |
| Fremont, CA, US | Dec 23, 04 - Dec 23, 04 |
Technology Profile
| Technology | Matters | |
|---|---|---|
| G06F: | ELECTRIC DIGITAL DATA PROCESSING | 3 |
| H03K: | PULSE TECHNIQUE | 1 |
| H04L: | TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION | 2 |
Patents / Publication
| Patents / Publication # | Year of Publication / Issued | Title | Citations |
|---|---|---|---|
| 7249273 | 2007 | Synchronized serial interface | 0 |
| 2005/0091,621 | 2005 | Methods for designing a circuit | 6 |
| 2004/0260,961 | 2004 | Synchronized serial interface | 3 |
| 2004/0230,933 | 2004 | Tool flow process for physical design of integrated circuits | 28 |
| 6625559 | 2003 | System and method for maintaining lock of a phase locked loop feedback during clock halt | 6 |
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