Krishna Garlapati
Inventor
Stats
- 5 US patents issued
- 14 US Applications filed
- most recent filing
This is official USPTO record data
Details
- 5 US Patents Issued
- 14 US Applications Filed
- 31 Total Citation Count
- Aug 29, 2023 Most Recent Filing
- Sep 7, 2001 Earliest Filing
Work History
Patent Owner | Applications Filed | Year |
---|---|---|
XILINX, INC. | 2
2 1 | 2013
2014 2016 |
SYNPLICITY | 1
| 2001
|
SYNOPSYS, INC. | 1
| 2001
|
Inventor Addresses
Address | Duration |
---|---|
Campbell, CA, US | Mar 04, 14 - Jan 12, 16 |
Los Gatos, CA, US | Feb 23, 16 - Mar 06, 25 |
Santa Clara, CA | Sep 09, 03 - Sep 09, 03 |
Technology Profile
Technology | Matters | |
---|---|---|
G01R: | MEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES | 2 |
G03F: | PHOTOMECHANICAL PRODUCTION OF TEXTURED OR PATTERNED SURFACES, e.g. FOR PRINTING, FOR PROCESSING OF SEMICONDUCTOR DEVICES; MATERIALS THEREFOR; ORIGINALS THEREFOR; APPARATUS SPECIALLY ADAPTED THEREFOR | 1 |
G06F: | ELECTRIC DIGITAL DATA PROCESSING | 14 |
Patents / Publication
Patents / Publication # | Year of Publication / Issued | Title | Citations |
---|---|---|---|
2025/0077,375 | 2025 | DEBUGGING PACKET PROCESSING PIPELINES IN PROGRAMMABLE NETWORK DEVICES | 0 |
2024/0370,242 | 2024 | REGISTER ALLOCATION OPTIMIZATION USING PER-REGISTER BIN PACKING | 0 |
2023/0096,887 | 2023 | PREDICATED PACKET PROCESSING IN NETWORK SWITCHING DEVICES | 0 |
2022/0261,523 | 2022 | BEHAVIORAL-LEVEL TIMING AND AREA OPTIMIATION | 0 |
11188697 | 2021 | On-chip memory access pattern detection for power and resource reduction | 0 |
We are sorry but your current selection exceeds the maximum number of portfolios (0) for this membership level.
>
Upgrade to our Level for up to -1 portfolios!.