Pierre-Emmanuel GAILLARDON
Inventor
Stats
- 2 US patents issued
- 11 US Applications filed
- most recent filing
This is official USPTO record data
Details
- 2 US Patents Issued
- 11 US Applications Filed
- 27 Total Citation Count
- Aug 29, 2024 Most Recent Filing
- Mar 14, 2012 Earliest Filing
Work History
| Patent Owner | Applications Filed | Year |
|---|---|---|
| COMMISSARIAT A L'ENERGIE ATOMIQUE ET AUX ENERGIES ALTERNATIVES | 2
| 2012
|
| ECOLE POLYTECHNIQUE FEDERALE DE LAUSANNE (EPFL) | 2
| 2014
|
| INSTITUT POLYTECHNIQUE DE GRENOBLE | 2
| 2012
|
Inventor Addresses
| Address | Duration |
|---|---|
| Renens, CH | Jan 28, 16 - Mar 01, 16 |
| Romans, FR | Sep 20, 12 - Oct 14, 14 |
| Salt Lake City, UT, US | Mar 26, 20 - Mar 06, 25 |
Technology Profile
| Technology | Matters | |
|---|---|---|
| G01D: | MEASURING NOT SPECIALLY ADAPTED FOR A SPECIFIC VARIABLE; ARRANGEMENTS FOR MEASURING TWO OR MORE VARIABLES NOT COVERED BY A SINGLE OTHER SUBCLASS; TARIFF METERING APPARATUS; MEASURING OR TESTING NOT OTHERWISE PROVIDED FOR | 1 |
| G06F: | ELECTRIC DIGITAL DATA PROCESSING | 5 |
| G06N: | COMPUTER SYSTEMS BASED ON SPECIFIC COMPUTATIONAL MODELS | 2 |
Patents / Publication
| Patents / Publication # | Year of Publication / Issued | Title | Citations |
|---|---|---|---|
| 2025/0080,087 | 2025 | PARASITIC CAPACITANCE MITIGATION CIRCUIT FOR RELAXATION OSCILLATORS | 0 |
| 12117316 | 2024 | Resistive sensor interface | 0 |
| 12112820 | 2024 | Single event effect mitigation with smart-redundancy | 0 |
| 2024/0255,315 | 2024 | RESISTIVE SENSOR INTERFACE | 0 |
| 2024/0232,497 | 2024 | Method for Generating Placement and Routing for an Integrated Circuit (IC) | 0 |
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