Jiewen Fan
Inventor
Stats
- 17 US patents issued
- 22 US Applications filed
- most recent filing
This is official USPTO record data
Details
- 17 US Patents Issued
- 22 US Applications Filed
- 103 Total Citation Count
- Mar 23, 2016 Most Recent Filing
- Apr 1, 2011 Earliest Filing
Work History
| Patent Owner | Applications Filed | Year |
|---|---|---|
| SEMICONDUCTOR MANUFACTURING INTERNATIONAL (SHANGHAI) CORPORATION | 10
1 | 2011
2012 |
| PEKING UNIVERSITY | 11
5 5 5 2 1 | 2011
2012 2013 2014 2015 2016 |
Inventor Addresses
| Address | Duration |
|---|---|
| Beijing, CN | Jul 26, 12 - Nov 22, 16 |
Technology Profile
| Technology | Matters | |
|---|---|---|
| B82Y: | SPECIFIC USES OR APPLICATIONS OF NANO-STRUCTURES; MEASUREMENT OR ANALYSIS OF NANO-STRUCTURES; MANUFACTURE OR TREATMENT OF NANO-STRUCTURES | 7 |
| G01R: | MEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES | 2 |
| G03F: | PHOTOMECHANICAL PRODUCTION OF TEXTURED OR PATTERNED SURFACES, e.g. FOR PRINTING, FOR PROCESSING OF SEMICONDUCTOR DEVICES; MATERIALS THEREFOR; ORIGINALS THEREFOR; APPARATUS SPECIALLY ADAPTED THEREFOR | 1 |
Patents / Publication
| Patents / Publication # | Year of Publication / Issued | Title | Citations |
|---|---|---|---|
| 9502310 | 2016 | Integration method for a vertical nanowire transistor | 1 |
| 9478641 | 2016 | Method for fabricating FinFET with separated double gates on bulk silicon | 2 |
| 2016/0268,384 | 2016 | METHOD FOR PREPARING A NANO-SCALE FIELD-EFFECT TRANSISTOR | 0 |
| 2016/0247,726 | 2016 | METHOD FOR FABRICATING A QUASI-SOI SOURCE-DRAIN MULTI-GATE DEVICE | 7 |
| 9425060 | 2016 | Method for fabricating multiple layers of ultra narrow silicon wires | 0 |
We are sorry but your current selection exceeds the maximum number of portfolios (0) for this membership level.
>
Upgrade to our Level for up to -1 portfolios!.