John W Cooksey
Inventor
Stats
- 7 US patents issued
- 7 US Applications filed
- most recent filing
This is official USPTO record data
Details
- 7 US Patents Issued
- 7 US Applications Filed
- 38 Total Citation Count
- Aug 26, 2016 Most Recent Filing
- May 20, 2005 Earliest Filing
Work History
| Patent Owner | Applications Filed | Year |
|---|---|---|
| SILICON STORAGE TECHNOLOGY, INC. | 4
2 1 2 1 1 | 2005
2006 2007 2010 2014 2016 |
| JPMORGAN CHASE BANK, N.A. | 1
1 1 | 2007
2014 2016 |
Inventor Addresses
| Address | Duration |
|---|---|
| Brentwood, CA | Jan 25, 07 - Oct 11, 07 |
| Brentwood, CA, US | Nov 23, 06 - Feb 13, 18 |
Technology Profile
| Technology | Matters | |
|---|---|---|
| G11C: | STATIC STORES | 4 |
| H01L: | SEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR | 5 |
Patents / Publication
| Patents / Publication # | Year of Publication / Issued | Title | Citations |
|---|---|---|---|
| 9892790 | 2018 | Method of programming a continuous-channel flash memory device | 0 |
| 2017/0032,846 | 2017 | Split Gate NAND Flash Memory Structure And Array, Method Of Programming, Erasing And Reading Thereof, And Method Of Manufacturing | 0 |
| 9449693 | 2016 | Split gate NAND flash memory structure and array, method of programming, erasing and reading thereof, and method of manufacturing | 2 |
| 2014/0340,967 | 2014 | Split Gate NAND Flash Memory Structure And Array, Method Of Programming, Erasing And Reading Thereof, And Method Of Manufacturing | 0 |
| 8780642 | 2014 | Split gate NAND flash memory structure and array, method of programming, erasing and reading thereof, and method of manufacturing | 3 |
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