Michael L Chu
Inventor
Stats
- 7 US patents issued
- 23 US Applications filed
- most recent filing
This is official USPTO record data
Details
- 7 US Patents Issued
- 23 US Applications Filed
- 68 Total Citation Count
- Jun 17, 2024 Most Recent Filing
- Jun 18, 2009 Earliest Filing
Work History
| Patent Owner | Applications Filed | Year |
|---|---|---|
| ADVANCED MICRO DEVICES, INC. | 2
| 2014
|
| MICROSOFT CORPORATION | 3
| 2017
|
| MICROSOFT TECHNOLOGY LICENSING, LLC | 2
10 3 | 2009
2010 2017 |
Inventor Addresses
| Address | Duration |
|---|---|
| Bellevue, WA, US | Dec 23, 10 - Mar 17, 20 |
| SANTA CLARA, CA, US | Jun 22, 23 - Nov 28, 24 |
| San Jose, CA, US | Nov 06, 14 - Jan 02, 25 |
| Santa Clara, CA, US | Aug 22, 19 - Dec 03, 24 |
Technology Profile
| Technology | Matters | |
|---|---|---|
| G06F: | ELECTRIC DIGITAL DATA PROCESSING | 23 |
| G06N: | COMPUTER SYSTEMS BASED ON SPECIFIC COMPUTATIONAL MODELS | 1 |
| G06T: | IMAGE DATA PROCESSING OR GENERATION, IN GENERAL | 1 |
Patents / Publication
| Patents / Publication # | Year of Publication / Issued | Title | Citations |
|---|---|---|---|
| 2025/0004,730 | 2025 | Selecting Intermediate Representation Transformations for Compilations | 0 |
| 12158842 | 2024 | Data co-location using address hashing for high-performance processing in memory | 0 |
| 2024/0394,199 | 2024 | VIRTUAL PARTITIONING A PROCESSOR-IN-MEMORY ("PIM") | 0 |
| 12067642 | 2024 | Memory latency-aware GPU architecture | 0 |
| 2024/0272,791 | 2024 | Automatic Data Layout for Operation Chains | 0 |
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