Seng Guan Chow
Inventor
Stats
- 203 US patents issued
- 216 US Applications filed
- most recent filing
This is official USPTO record data
Details
- 203 US Patents Issued
- 216 US Applications Filed
- 5443 Total Citation Count
- Sep 2, 2020 Most Recent Filing
- May 30, 2001 Earliest Filing
Work History
Patent Owner | Applications Filed | Year |
---|---|---|
St Assembly Test Services Pte Ltd | 4
3 2 | 2001
2002 2003 |
STATS CHIPPAC LTD. | 1
2 6 1 1 3 | 2008
2010 2011 2012 2014 2015 |
STATS CHIPPAC, INC. | 2
6 4 | 2006
2007 2009 |
ST ASSEMBLY TEST SERVICES LTD. | 2
| 2003
|
STATS CHIPPAC PTE. LTE. | 4
3 8 10 15 59 53 68 40 51 35 22 7 8 4 1 2 | 2001
2002 2003 2004 2005 2006 2007 2008 2009 2010 2011 2012 2013 2014 2015 2016 2017 |
Inventor Addresses
Address | Duration |
---|---|
Sigapore, SG | Jan 24, 08 - Jan 24, 08 |
Singapore, SG | Dec 05, 02 - Sep 03, 24 |
Technology Profile
Technology | Matters | |
---|---|---|
B28B: | SHAPING CLAY OR OTHER CERAMIC COMPOSITIONS, SLAG OR MIXTURES CONTAINING CEMENTITIOUS MATERIAL, e.g. PLASTER | 1 |
B29C: | SHAPING OR JOINING OF PLASTICS; SHAPING OF SUBSTANCES IN A PLASTIC STATE, IN GENERAL; AFTER- TREATMENT OF THE SHAPED PRODUCTS, e.g. REPAIRING | 2 |
B81C: | PROCESSES OR APPARATUS SPECIALLY ADAPTED FOR THE MANUFACTURE OR TREATMENT OF MICRO-STRUCTURAL DEVICES OR SYSTEMS | 1 |
Patents / Publication
Patents / Publication # | Year of Publication / Issued | Title | Citations |
---|---|---|---|
12080600 | 2024 | Semiconductor device and method to minimize stress on stack via | 0 |
RE48408 | 2021 | Semiconductor device and method of forming interposer frame over semiconductor die to provide vertical interconnect | 0 |
2020/0402,855 | 2020 | Semiconductor Device and Method to Minimize Stress on Stack Via | 0 |
10804153 | 2020 | Semiconductor device and method to minimize stress on stack via | 1 |
RE48111 | 2020 | Semiconductor device and method of forming interposer frame over semiconductor die to provide vertical interconnect | 1 |
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