Jangseok Choi
Inventor
Stats
- 2 US patents issued
- 31 US Applications filed
- most recent filing
This is official USPTO record data
Details
- 2 US Patents Issued
- 31 US Applications Filed
- 182 Total Citation Count
- Oct 16, 2024 Most Recent Filing
- Jan 21, 2010 Earliest Filing
Work History
| Patent Owner | Applications Filed | Year |
|---|---|---|
| SAMSUNG ELECTRONICS CO., LTD. | 2
1 1 6 | 2010
2012 2013 2016 |
Inventor Addresses
| Address | Duration |
|---|---|
| Campbell, CA, US | Sep 07, 17 - Mar 04, 25 |
| Hwasung, KR | Jul 09, 19 - Jul 09, 19 |
| Hwasung-City, KR | Dec 21, 17 - Dec 21, 17 |
| Hwasung-Si, KR | May 10, 18 - Feb 02, 21 |
| SEONGNAM-SI, KR | Jul 08, 21 - Mar 24, 22 |
| San Jose, CA, US | Sep 07, 17 - Jul 09, 24 |
| Seongnam-si, KR | May 06, 21 - Nov 30, 23 |
| Seoul, KR | Aug 26, 10 - Oct 03, 13 |
| Suwon-si, KR | Mar 25, 21 - Apr 01, 25 |
Technology Profile
| Technology | Matters | |
|---|---|---|
| G06F: | ELECTRIC DIGITAL DATA PROCESSING | 22 |
| G11C: | STATIC STORES | 20 |
| H01L: | SEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR | 2 |
Patents / Publication
| Patents / Publication # | Year of Publication / Issued | Title | Citations |
|---|---|---|---|
| 12265488 | 2025 | Apparatus and method for die-to-die (D2D) interconnects | 0 |
| 12242344 | 2025 | DRAM assist error correction mechanism for DDR SDRAM interface | 0 |
| 2025/0036,584 | 2025 | ASYNCHRONOUS COMMUNICATION PROTOCOL COMPATIBLE WITH SYNCHRONOUS DDR PROTOCOL | 0 |
| 12189546 | 2025 | Asynchronous communication protocol compatible with synchronous DDR protocol | 0 |
| 12147360 | 2024 | Asynchronous communication protocol compatible with synchronous DDR protocol | 0 |
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