Hareesh CHANDRASEKAR
Inventor
Stats
- 0 US patents issued
- 2 US Applications filed
- most recent filing
This is official USPTO record data
Details
- 0 US Patents Issued
- 2 US Applications Filed
- 0 Total Citation Count
- Mar 18, 2021 Most Recent Filing
- Mar 17, 2017 Earliest Filing
Work History
| Patent Owner | Applications Filed | Year |
|---|---|---|
| INDIAN INSTITUTE OF SCIENCE | 1
| 2017
|
Inventor Addresses
| Address | Duration |
|---|---|
| BANGALORE, IN | Sep 28, 17 - Sep 28, 17 |
| Bangalore, IN | Dec 01, 20 - Dec 01, 20 |
| Columbus, OH, US | Dec 19, 23 - Dec 19, 23 |
Technology Profile
| Technology | Matters | |
|---|---|---|
| C30B: | SINGLE-CRYSTAL GROWTH | 1 |
| H01L: | SEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR | 2 |
Patents / Publication
| Patents / Publication # | Year of Publication / Issued | Title | Citations |
|---|---|---|---|
| 11848359 | 2023 | Method of forming lateral pn junctions in III-nitrides using p-type and n-type co-doping and selective p-type activation and deactivation | 0 |
| 10854719 | 2020 | Platform of large metal nitride islands with lateral orientations and low-defect density | 0 |
| 2017/0278,932 | 2017 | PLATFORM OF LARGE METAL NITRIDE ISLANDS WITH LATERAL ORIENTATIONS AND LOW-DEFECT DENSITY | 0 |
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