Edward Burton
Inventor
Stats
- 17 US patents issued
- 29 US Applications filed
- most recent filing
This is official USPTO record data
Details
- 17 US Patents Issued
- 29 US Applications Filed
- 461 Total Citation Count
- Apr 19, 2024 Most Recent Filing
- Jan 8, 1999 Earliest Filing
Work History
Patent Owner | Applications Filed | Year |
---|---|---|
SONY CORPORATION OF AMERICA | 4
2 2 | 2006
2009 2010 |
INTEL CORPORATION | 1
8 12 1 3 | 1999
2005 2006 2008 2009 |
ISIS INNOVATION LIMITED | 1
| 2000
|
Inventor Addresses
Address | Duration |
---|---|
Hillsboro, OR | Jan 16, 01 - Dec 16, 08 |
Hillsboro, OR, US | Dec 07, 06 - Dec 10, 24 |
Huntingdon, Cambridgeshire, GB | Nov 02, 23 - Nov 02, 23 |
Pittsburgh, PA | Apr 17, 07 - Apr 17, 07 |
Technology Profile
Technology | Matters | |
---|---|---|
B41J: | TYPEWRITERS; SELECTIVE PRINTING MECHANISMS, i.e. MECHANISMS PRINTING OTHERWISE THAN FROM A FORME; CORRECTION OF TYPOGRAPHICAL ERRORS | 1 |
C12P: | FERMENTATION OR ENZYME-USING PROCESSES TO SYNTHESISE A DESIRED CHEMICAL COMPOUND OR COMPOSITION OR TO SEPARATE OPTICAL ISOMERS FROM A RACEMIC MIXTURE | 1 |
G05F: | SYSTEMS FOR REGULATING ELECTRIC OR MAGNETIC VARIABLES | 8 |
Patents / Publication
Patents / Publication # | Year of Publication / Issued | Title | Citations |
---|---|---|---|
12164319 | 2024 | Dual loop voltage regulator | 0 |
12100662 | 2024 | Power-forwarding bridge for inter-chip data signal transfer | 0 |
2024/0266,323 | 2024 | STACKED SEMICONDUCTOR DIE ARCHITECTURE WITH MULTIPLE LAYERS OF DISAGGREGATION | 0 |
12015009 | 2024 | Stacked semiconductor die architecture with multiple layers of disaggregation | 0 |
2023/0347,648 | 2023 | AN ACTUATOR COMPONENT FOR A DROPLET EJECTION HEAD AND METHOD FOR MANUFACTURING THE SAME | 0 |
We are sorry but your current selection exceeds the maximum number of portfolios (0) for this membership level.
>
Upgrade to our Level for up to -1 portfolios!.