Daniel B Aubertine
Inventor
Stats
- 14 US patents issued
- 26 US Applications filed
- most recent filing
This is official USPTO record data
Details
- 14 US Patents Issued
- 26 US Applications Filed
- 642 Total Citation Count
- Jul 22, 2024 Most Recent Filing
- Mar 28, 2007 Earliest Filing
Work History
| Patent Owner | Applications Filed | Year |
|---|---|---|
| INTEL CORPORATION | 2
3 8 2 6 6 2 2 | 2007
2008 2012 2013 2014 2015 2016 2017 |
Inventor Addresses
| Address | Duration |
|---|---|
| North Plains, OR | Oct 02, 08 - Oct 02, 08 |
| North Plains, OR, US | Dec 31, 09 - Nov 14, 24 |
Technology Profile
| Technology | Matters | |
|---|---|---|
| B82Y: | SPECIFIC USES OR APPLICATIONS OF NANO-STRUCTURES; MEASUREMENT OR ANALYSIS OF NANO-STRUCTURES; MANUFACTURE OR TREATMENT OF NANO-STRUCTURES | 1 |
| C09K: | MATERIALS FOR APPLICATIONS NOT OTHERWISE PROVIDED FOR; APPLICATIONS OF MATERIALS NOT OTHERWISE PROVIDED FOR | 1 |
| H01L: | SEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR | 26 |
Patents / Publication
| Patents / Publication # | Year of Publication / Issued | Title | Citations |
|---|---|---|---|
| 2024/0379,453 | 2024 | SELF-ALIGNED 3-D EPITAXIAL STRUCTURES FOR MOS DEVICE FABRICATION | 0 |
| 12046517 | 2024 | Self-aligned 3-D epitaxial structures for MOS device fabrication | 0 |
| 2022/0028,747 | 2022 | SELF-ALIGNED 3-D EPITAXIAL STRUCTURES FOR MOS DEVICE FABRICATION | 0 |
| 11171058 | 2021 | Self-aligned 3-D epitaxial structures for MOS device fabrication | 0 |
| 10879241 | 2020 | Techniques for controlling transistor sub-fin leakage | 0 |
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