Ishwar AGARWAL
Inventor
Stats
- 4 US patents issued
- 57 US Applications filed
- most recent filing
This is official USPTO record data
Details
- 4 US Patents Issued
- 57 US Applications Filed
- 285 Total Citation Count
- Dec 12, 2024 Most Recent Filing
- Sep 26, 2014 Earliest Filing
Work History
| Patent Owner | Applications Filed | Year |
|---|---|---|
| INTEL CORPORATION | 2
3 1 | 2014
2015 2016 |
Inventor Addresses
| Address | Duration |
|---|---|
| Hillsboro, OR, US | Mar 31, 16 - Oct 10, 23 |
| Hisslboro, OR, US | Apr 17, 18 - Apr 17, 18 |
| Portland, OR, US | Feb 07, 19 - Nov 14, 23 |
| Redmond, WA, US | Dec 28, 21 - Apr 03, 25 |
Technology Profile
| Technology | Matters | |
|---|---|---|
| G01R: | MEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES | 1 |
| G06F: | ELECTRIC DIGITAL DATA PROCESSING | 55 |
| G06N: | COMPUTER SYSTEMS BASED ON SPECIFIC COMPUTATIONAL MODELS | 1 |
Patents / Publication
| Patents / Publication # | Year of Publication / Issued | Title | Citations |
|---|---|---|---|
| 2025/0110,829 | 2025 | MEMORY TIERING TECHNIQUES IN COMPUTING SYSTEMS | 0 |
| 2025/0111,048 | 2025 | DETECTING AND MITIGATING MEMORY ATTACKS | 0 |
| 2025/0103,339 | 2025 | DIRECT SWAP CACHING WITH ZERO LINE OPTIMIZATIONS | 0 |
| 12259973 | 2025 | Systems and methods for flush plus reload cache side-channel attack mitigation | 0 |
| 12242376 | 2025 | Paging in thin-provisioned disaggregated memory | 0 |
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