VIA ALLIANCE SEMICONDUCTOR CO., LTD.

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Patent Activity in the Last 10 Years

Technologies

Intl Class Technology Matters Rank in Class
 
  
 
G06F ELECTRIC DIGITAL DATA PROCESSING 158293
 
  
 
G11C STATIC STORES 39112
 
  
 
H03K PULSE TECHNIQUE 20111
 
  
 
G06N COMPUTER SYSTEMS BASED ON SPECIFIC COMPUTATIONAL MODELS 1749
 
  
 
G06T IMAGE DATA PROCESSING OR GENERATION, IN GENERAL 16119
 
  
 
H03M CODING, DECODING OR CODE CONVERSION, IN GENERAL 1299
 
  
 
H04N PICTORIAL COMMUNICATION, e.g. TELEVISION 12230
 
  
 
H01L SEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR 10352
 
  
 
H03L AUTOMATIC CONTROL, STARTING, SYNCHRONISATION, OR STABILISATION OF GENERATORS OF ELECTRONIC OSCILLATIONS OR PULSES 971
 
  
 
H04L TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION 8277

Top Patents (by citation)

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Recent Publications

Publication # Title Filing Date Pub Date Intl Class
2018/0061,672 CHIP PACKAGE PROCESSJun 29, 17Mar 01, 18[H01L]
2017/0315,921 CACHE MEMORY BUDGETED BY WAYS BASED ON MEMORY ACCESS TYPEDec 14, 14Nov 02, 17[G06F]
2017/0168,723 HOST INTERFACE CONTROLLER AND CONTROL METHOD FOR STORAGE DEVICEMay 20, 16Jun 15, 17[G06F]
2017/0161,067 PROCESSOR WITH AN EXPANDABLE INSTRUCTION SET ARCHITECTURE FOR DYNAMICALLY CONFIGURING EXECUTION RESOURCESOct 28, 16Jun 08, 17[G06F]
2017/0103,304 NEURAL NETWORK UNIT WITH PLURALITY OF SELECTABLE OUTPUT FUNCTIONSApr 05, 16Apr 13, 17[G06N]
2017/0103,311 NEURAL NETWORK UNIT THAT PERFORMS CONVOLUTIONS USING COLLECTIVE SHIFT REGISTER AMONG ARRAY OF NEURAL PROCESSING UNITSApr 05, 16Apr 13, 17[G06N]
2017/0060,581 SYSTEM AND METHOD OF ACCELERATING ARBITRATION BY APPROXIMATING RELATIVE AGESAug 19, 16Mar 02, 17[G06F]
2016/0357,664 MULTI-MODE SET ASSOCIATIVE CACHE MEMORY DYNAMICALLY CONFIGURABLE TO SELECTIVELY ALLOCATE INTO ALL OR A SUBSET OF ITS WAYS DEPENDING ON THE MODEDec 14, 14Dec 08, 16[G06F]
2016/0350,229 DYNAMIC CACHE REPLACEMENT WAY SELECTION BASED ON ADDRESS TAG BITSDec 14, 14Dec 01, 16[G06F]
2016/0350,537 CENTRAL PROCESSING UNIT AND METHOD TO VERIFY MAINBOARD DATAApr 14, 16Dec 01, 16[H04L, G06F]

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Recent Patents

Patent # Title Filing Date Issue Date Intl Class
9915998 Power saving mechanism to reduce load replays in out-of-order processorNov 24, 15Mar 13, 18[G06F]
9910598 Host interface controller and control method for storage deviceMay 20, 16Mar 06, 18[G06F, G11C]
9910785 Cache memory budgeted by ways based on memory access typeDec 14, 14Mar 06, 18[G06F]
9911508 Cache memory diagnostic writebackNov 26, 14Mar 06, 18[G06F, G11C]
9912351 Methods for accelerating hash-based compression and apparatuses using the sameAug 10, 17Mar 06, 18[H03M, G06F]
9904550 Methods for combining instructions and apparatuses having multiple data pipesSep 16, 15Feb 27, 18[G06F]
9905519 Electronic structure processJun 29, 17Feb 27, 18[H01L]
9898411 Cache memory budgeted by chunks based on memory access typeDec 14, 14Feb 20, 18[G06F]
9898418 Processor including single invalidate page instructionMay 21, 15Feb 20, 18[G06F]
9900008 Pre-driver and replica circuit and driver system with the sameMay 15, 17Feb 20, 18[H03K]

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Expired/Abandoned/Withdrawn Patents

Patent # Title Status Filing Date Issue/Pub Date Intl Class
2016/0259,728 CACHE SYSTEM WITH A PRIMARY CACHE AND AN OVERFLOW FIFO CACHEAbandonedDec 12, 14Sep 08, 16[G06F]

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