STMICROELECTRONICS (CROLLES 2) SAS
Patent Owner
Stats
- 588 US PATENTS IN FORCE
- 25 US APPLICATIONS PENDING
- Mar 20, 2018 most recent publication
Details
- 588 Issued Patents
- 0 Issued in last 3 years
- 0 Published in last 3 years
- 6,823 Total Citation Count
- Dec 16, 2004 Earliest Filing
- 95 Expired/Abandoned/Withdrawn Patents
Patent Activity in the Last 10 Years
Technologies
Intl Class
Technology
Matters
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Top Patents (by citation)
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Recent Publications
Publication #
Title
Filing Date
Pub Date
Intl Class
2018/0061,875 VERTICAL TRANSFER GATE TRANSISTOR AND ACTIVE CMOS IMAGE SENSOR PIXEL INCLUDING A VERTICAL TRANSFER GATE TRANSISTORAug 30, 16Mar 01, 18[H01L, H04N]
2017/0317,106 MOS TRANSISTOR STRUCTURE, IN PARTICULAR FOR HIGH VOLTAGES USING A TECHNOLOGY OF THE SILICON-ON-INSULATOR TYPENov 28, 16Nov 02, 17[H01L]
2017/0288,781 HIGHER ORDER OPTICAL PAM MODULATION USING A MACH-ZEHNDER INTERFEROMETER (MZI) TYPE OPTICAL MODULATOR HAVING A BENT OPTICAL PATHMar 29, 16Oct 05, 17[H04L, H04B]
2017/0271,470 METHOD FOR FABRICATION OF A FIELD-EFFECT WITH REDUCED STRAY CAPACITANCEMar 21, 17Sep 21, 17[H01L]
Recent Patents
Patent #
Title
Filing Date
Issue Date
Intl Class
9922871 Process for producing a contact on an active zone of an integrated circuit, for example produced on an SOI substrate, in particular an FDSOI substrate, and corresponding integrated circuitJan 09, 17Mar 20, 18[H01L]
9917126 Metal shield trenches and metal substrate contacts supported within the premetallization dielectric (PMD) layer of an integrated circuit using a middle end of line (MEOL) processSep 13, 16Mar 13, 18[H01L]
9911820 Method for fabrication of a field-effect with reduced stray capacitanceMar 21, 17Mar 06, 18[H01L]
9876076 Method for local isolation between transistors produced on an SOI substrate, in particular an FDSOI substrate, and corresponding integrated circuitDec 02, 15Jan 23, 18[H01L]
Expired/Abandoned/Withdrawn Patents
Patent #
Title
Status
Filing Date
Issue/Pub Date
Intl Class
2017/0194,350 LOW-NOISE MOS TRANSISTORS AND CORRESPONDING CIRCUITAbandonedApr 25, 16Jul 06, 17[H01L]
2016/0351,661 PROCESS FOR PRODUCING MOS TRANSISTORS HAVING A LARGER CHANNEL WIDTH FROM AN SOI AND IN PARTICULAR FDSOI SUBSTRATE, AND CORRESPONDING INTEGRATED CIRCUITAbandonedDec 08, 15Dec 01, 16[H01L]
2016/0284,807 METHOD OF FORMATION OF A SUBSTRATE OF THE SOI, IN PARTICULAR THE FDSOI, TYPE ADAPTED TO TRANSISTORS HAVING GATE DIELECTRICS OF DIFFERENT THICKNESSES, CORRESPONDING SUBSTRATE AND INTEGRATED CIRCUITAbandonedNov 02, 15Sep 29, 16[H01L]
2016/0181,382 METHOD FOR FABRICATING A TRANSISTOR WITH A RAISED SOURCE-DRAIN STRUCTUREAbandonedDec 19, 14Jun 23, 16[H01L]
2016/0099,183 METHOD FOR RELAXING THE TRANSVERSE MECHANICAL STRESSES WITHIN THE ACTIVE REGION OF A MOS TRANSISTOR, AND CORRESPONDING INTEGRATED CIRCUITAbandonedDec 11, 15Apr 07, 16[H01L]
2015/0300,328 THERMOELECTRIC GENERATOR COMPRISING A DEFORMABLE BY-LAYER MEMBRANE EXHIBITING MAGNETIC PROPERTIESAbandonedApr 14, 15Oct 22, 15[H02N, F03G]
2015/0255,540 COMPONENT, FOR EXAMPLE NMOS TRANSISTOR, WITH ACTIVE REGION WITH RELAXED COMPRESSION STRESSES, AND FABRICATION METHODAbandonedMay 18, 15Sep 10, 15[H01L]
2015/0137,133 FORMING OF A HEAVILY-DOPED SILICON LAYER ON A MORE LIGHTLY-DOPED SILICON SUBSTRATEAbandonedNov 11, 14May 21, 15[H01L]
2015/0097,241 METHOD FOR RELAXING THE TRANSVERSE MECHANICAL STRESSES WITHIN THE ACTIVE REGION OF A MOS TRANSISTOR, AND CORRESPONDING INTEGRATED CIRCUITAbandonedOct 03, 14Apr 09, 15[H01L]
2015/0022,987 ELECTRONIC DEVICE COMPRISING AN INTEGRATED CIRCUIT CHIP PROVIDED WITH PROJECTING ELECTRICAL CONNECTION PADSAbandonedJul 14, 14Jan 22, 15[H05K]
2014/0376,857 PHOTONIC INTEGRATED CIRCUIT AND FABRICATION PROCESSAbandonedJun 23, 14Dec 25, 14[G02B]
2014/0206,154 SEMICONDUCTOR DEVICE COMPRISING A PASSIVE COMPONENT OF CAPACITORS AND PROCESS FOR FABRICATIONAbandonedMar 21, 14Jul 24, 14[H01L]
2014/0106,529 FINFET DEVICE WITH SILICIDED SOURCE-DRAIN REGIONS AND METHOD OF MAKING SAME USING A TWO STEP ANNEALAbandonedOct 10, 13Apr 17, 14[H01L]
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