RISE TECHNOLOGY COMPANY
Patent Owner
Stats
- 0 US PATENTS IN FORCE
- 0 US APPLICATIONS PENDING
- Jun 18, 2002 most recent publication
Details
- 0 Issued Patents
- 0 Issued in last 3 years
- 0 Published in last 3 years
- 132 Total Citation Count
- Apr 06, 1998 Earliest Filing
- 15 Expired/Abandoned/Withdrawn Patents
Patent Activity in the Last 10 Years
Technologies
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Recent Publications
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Recent Patents
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Expired/Abandoned/Withdrawn Patents
Patent #
Title
Status
Filing Date
Issue/Pub Date
Intl Class
6408377 Dynamic allocation of resources in multiple microprocessor pipelinesExpiredApr 26, 01Jun 18, 02[G06F]
6341343 Parallel processing instructions routed through plural differing capacity units of operand address generators coupled to multi-ported memory and ALUsExpiredApr 26, 01Jan 22, 02[G06F]
6321300 Apparatus and method for dynamically reconfigurable timed flushing of a queue of coalescing write buffersExpiredMay 14, 99Nov 20, 01[G06F]
6311298 Mechanism to simplify built-in self test of a control store unitExpiredFeb 17, 99Oct 30, 01[G06F, G11C]
6304954 Executing multiple instructions in multi-pipelined processor by dynamically switching memory ports of fewer number than the pipelineExpiredSep 11, 98Oct 16, 01[G06F]
6304956 Using two barrel shifters to implement shift, rotate, rotate with carry, and shift double as specified by the X86 architectureExpiredMar 25, 99Oct 16, 01[G06F]
6289439 Method, device and microprocessor for performing an XOR clear without executing an XOR instructionExpiredJan 08, 99Sep 11, 01[G06F]
2001/0014,940 Dynamic allocation of resources in multiple microprocessor pipelinesAbandonedApr 26, 01Aug 16, 01[G06F]
6263424 Execution of data dependent arithmetic instructions in multi-pipeline processorsExpiredAug 03, 98Jul 17, 01[G06F]
6233675 Facility to allow fast execution of and, or, and test instructionsExpiredMar 25, 99May 15, 01[G06F]
6223257 Instruction cache address generation technique having reduced delays in fetching missed dataExpiredMay 12, 99Apr 24, 01[G06F]
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