PROMOS TECHNOLOGIES PTE. LTD.
Patent Owner
Stats
- 0 US PATENTS IN FORCE
- 0 US APPLICATIONS PENDING
- Mar 18, 2010 most recent publication
Details
- 0 Issued Patents
- 0 Issued in last 3 years
- 0 Published in last 3 years
- 457 Total Citation Count
- Sep 12, 2005 Earliest Filing
- 28 Expired/Abandoned/Withdrawn Patents
Patent Activity in the Last 10 Years
Technologies
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Top Patents (by citation)
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Recent Publications
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Recent Patents
- No Recent Patents to Display
Expired/Abandoned/Withdrawn Patents
Patent #
Title
Status
Filing Date
Issue/Pub Date
Intl Class
2010/0068,658 PHOTOLITHOGRAPHIC PATTERNING OF ARRAYS OF PILLARS HAVING WIDTHS AND LENGTHS BELOW THE EXPOSURE WAVELENGTHSAbandonedSep 18, 08Mar 18, 10[G03F]
2010/0059,808 NONVOLATILE MEMORIES WITH CHARGE TRAPPING DIELECTRIC MODIFIED AT THE EDGESAbandonedSep 10, 08Mar 11, 10[H01L]
2010/0063,764 USE OF DIFFERENT PAIRS OF OVERLAY LAYERS TO CHECK AN OVERLAY MEASUREMENT RECIPEAbandonedSep 10, 08Mar 11, 10[G01P]
2009/0321,806 NONVOLATILE MEMORY WITH FLOATING GATES WITH UPWARD PROTRUSIONSAbandonedJun 26, 08Dec 31, 09[H01L]
2009/0256,221 METHOD FOR MAKING VERY SMALL ISOLATED DOTS ON SUBSTRATESAbandonedApr 11, 08Oct 15, 09[H01L]
2009/0251,972 NONVOLATILE MEMORY ARRAYS WITH CHARGE TRAPPING DIELECTRIC AND WITH NON-DIELECTRIC NANODOTSAbandonedApr 03, 08Oct 08, 09[H01L, G11C]
2009/0184,359 Split-gate non-volatile memory devices having nitride tunneling layersAbandonedJan 22, 08Jul 23, 09[H01L]
2009/0140,318 NONVOLATILE MEMORIES WITH HIGHER CONDUCTION-BAND EDGE ADJACENT TO CHARGE-TRAPPING DIELECTRICAbandonedDec 03, 07Jun 04, 09[H01L]
2009/0127,723 AIM-Compatible Targets for Use with Methods of Inspecting and Optionally Reworking Summed Photolithography Patterns Resulting from Plurally-Overlaid Patterning Steps During Mass Production of Semiconductor DevicesAbandonedApr 14, 08May 21, 09[H01L, G01B, G03F]
2009/0096,009 NONVOLATILE MEMORIES WHICH COMBINE A DIELECTRIC, CHARGE-TRAPPING LAYER WITH A FLOATING GATEAbandonedOct 16, 07Apr 16, 09[H01L]
2009/0085,069 NAND-type Flash Array with Reduced Inter-cell Coupling ResistanceAbandonedSep 27, 07Apr 02, 09[H01L]
2009/0032,861 NONVOLATILE MEMORIES WITH CHARGE TRAPPING LAYERS CONTAINING SILICON NITRIDE WITH GERMANIUM OR PHOSPHORUSAbandonedJul 30, 07Feb 05, 09[H01L]
2008/0291,723 SOURCE BIASING OF NOR-TYPE FLASH ARRAY WITH DYNAMICALLY VARIABLE SOURCE RESISTANCEAbandonedMay 23, 07Nov 27, 08[H01L, G11C]
2008/0286,984 SILICON-RICH LOW-HYDROGEN CONTENT SILICON NITRIDE FILMAbandonedMay 14, 07Nov 20, 08[H01L]
2008/0204,102 METHOD TO REGULATE PROPAGATION DELAY OF CAPACITIVELY COUPLED PARALLEL LINESAbandonedFeb 27, 07Aug 28, 08[H03H]
Top Inventors for This Owner
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