POWERTECH TECHNOLOGY INC.

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Patent Activity in the Last 10 Years

Technologies

Intl Class Technology Matters Rank in Class
 
  
 
H01L SEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR 84279
 
  
 
G01R MEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES 3156
 
  
 
H05K PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS 3153
 
  
 
B23K SOLDERING OR UNSOLDERING; WELDING; CLADDING OR PLATING BY SOLDERING OR WELDING; CUTTING BY APPLYING HEAT LOCALLY, e.g. FLAME CUTTING; WORKING BY LASER BEAM 192
 
  
 
G06K RECOGNITION OF DATA; PRESENTATION OF DATA; RECORD CARRIERS; HANDLING RECORD CARRIERS 1197
 
  
 
G11C STATIC STORES 1150
 
  
 
H01R ELECTRICALLY-CONDUCTIVE CONNECTIONS; STRUCTURAL ASSOCIATIONS OF A PLURALITY OF MUTUALLY-INSULATED ELECTRICAL CONNECTING ELEMENTS; COUPLING DEVICES; CURRENT COLLECTORS 1132
 
  
 
H04B TRANSMISSION 1209
 
  
 
H04L TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION 1284

Top Patents (by citation)

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Recent Publications

Publication # Title Filing Date Pub Date Intl Class
2018/0076,179 STACKED TYPE CHIP PACKAGE STRUCTURE AND MANUFACTURING METHOD THEREOFJul 03, 17Mar 15, 18[H01L]
2017/0358,557 PACKAGE-ON-PACKAGE STRUCTURE AND MANUFACTURING METHOD THEREOFFeb 16, 17Dec 14, 17[H01L]
2017/0338,128 MANUFACTURING METHOD OF PACKAGE STRUCTUREMay 02, 17Nov 23, 17[H01L]
2017/0287,870 STACKED CHIP PACKAGE STRUCTURE AND MANUFACTURING METHOD THEREOFMar 10, 17Oct 05, 17[H01L]
2017/0194,231 BALL GRID ARRAY PACKAGE WITH PROTECTIVE CIRCUITRY LAYOUT AND A SUBSTRATE UTILIZED IN THE PACKAGEDec 20, 16Jul 06, 17[H01L]
2017/0186,711 STRUCTURE AND METHOD OF FAN-OUT STACKED PACKAGESDec 14, 16Jun 29, 17[H01L]
2017/0110,416 CHIP PACKAGE HAVING A PROTECTION PIECE COMPLIANTLY ATTACHED ON A CHIP SENSING SURFACEMay 20, 16Apr 20, 17[H01L, G06K]
2017/0084,513 SEMICONDUCTOR PACKAGEDec 05, 16Mar 23, 17[H01L]

Recent Patents

Patent # Title Filing Date Issue Date Intl Class
9899287 Fan-out wafer level package structureMar 27, 17Feb 20, 18[H01L]
9899307 Fan-out chip package with dummy pattern and its fabricating methodAug 24, 16Feb 20, 18[H01L]
9887148 Fan-out semiconductor package structure and fabricating methodFeb 21, 17Feb 06, 18[H01L]
9859187 Ball grid array package with protective circuitry layout and a substrate utilized in the packageDec 20, 16Jan 02, 18[H01L]
9859233 Semiconductor device package with reinforced redistribution layerDec 25, 16Jan 02, 18[H01L]
9853015 Semiconductor device with stacking chipsDec 15, 16Dec 26, 17[H01L]
9842811 Heat-dissipating semiconductor package for lessening package warpageNov 17, 16Dec 12, 17[H01L]
9837384 Fan-out multi-chip package with plurality of chips stacked in staggered stack arrangementAug 24, 16Dec 05, 17[H01L]
9837385 Substrate-less package structureMar 16, 17Dec 05, 17[H01L]
9831219 Manufacturing method of package structureApr 20, 17Nov 28, 17[H01L]

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Expired/Abandoned/Withdrawn Patents

Patent # Title Status Filing Date Issue/Pub Date Intl Class
2017/0229,426 FAN-OUT BACK-TO-BACK CHIP STACKED PACKAGES AND THE METHOD FOR MANUFACTURING THE SAMEAbandonedSep 27, 16Aug 10, 17[H01L]
2017/0117,263 MOLDED INTERCONNECTING SUBSTRATE AND THE METHOD FOR MANUFACTURING THE SAMEAbandonedJun 23, 16Apr 27, 17[H01L]
2017/0047,277 SEMICONDUCTOR STRUCTUREAbandonedApr 12, 16Feb 16, 17[H01L, H05K]
2016/0163,624 PACKAGE STRUCTUREAbandonedDec 09, 14Jun 09, 16[H01L]
2016/0099,202 SEMICONDUCTOR PACKAGING STRUCTUREAbandonedNov 20, 14Apr 07, 16[H01L]
2015/0091,154 SUBSTRATELESS PACKAGES WITH SCRIBE DISPOSED ON HEAT SPREADERAbandonedSep 30, 13Apr 02, 15[H01L]
2015/0048,496 FABRICATION PROCESS AND STRUCTURE TO FORM BUMPS ALIGNED ON TSV ON CHIP BACKSIDEAbandonedAug 13, 13Feb 19, 15[H01L]
2015/0048,499 FINE-PITCH PILLAR BUMP LAYOUT STRUCTURE ON CHIPAbandonedAug 16, 13Feb 19, 15[H01L]
2013/0075,881 MEMORY CARD PACKAGE WITH A SMALL SUBSTRATEAbandonedSep 23, 11Mar 28, 13[H01L]
2013/0069,223 FLASH MEMORY CARD WITHOUT A SUBSTRATE AND ITS FABRICATION METHODAbandonedSep 16, 11Mar 21, 13[H01L]
2013/0026,658 WAFER LEVEL CHIP SCALE PACKAGE FOR WIRE-BONDING CONNECTIONAbandonedJul 29, 11Jan 31, 13[H01L]
2013/0009,294 MULTI-CHIP PACKAGE HAVING LEADERFRAME-TYPE CONTACT FINGERSAbandonedJul 05, 11Jan 10, 13[H01L]
2012/0239,317 CONTROLLING DEVICE AND METHOD FOR ABNORMALITY PREDICTION OF SEMICONDUCTOR PROCESSING EQUIPMENTAbandonedJun 09, 11Sep 20, 12[G01N, G06F]
2012/0228,759 SEMICONDUCTOR PACKAGE HAVING INTERCONNECTION OF DUAL PARALLEL WIRESAbandonedMar 07, 11Sep 13, 12[H01L]
2012/0139,110 TAPEAbandonedDec 07, 11Jun 07, 12[H01L]
2012/0049,359 BALL GRID ARRAY PACKAGEAbandonedAug 30, 10Mar 01, 12[H01L]
2012/0052,630 METHOD FOR MANUFACTURING CHIP PACKAGEAbandonedMar 23, 11Mar 01, 12[H01L]
8115319 Flip chip package maintaining alignment during solderingExpiredMar 04, 10Feb 14, 12[H01L]
2011/0304,041 ELECTRICALLY CONNECTING ROUTES OF SEMICONDUCTOR CHIP PACKAGE CONSOLIDATED IN DIE-ATTACHMENTAbandonedJul 07, 10Dec 15, 11[H01L]
2011/0304,044 STACKED CHIP PACKAGE STRUCTURE AND ITS FABRICATION METHODAbandonedJul 07, 10Dec 15, 11[H01L]

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